I found that both processor event based sampling and precise event based sampling abbreviate to "PEBS". So what the difference between them? When people using "PEBS", how can I know it means processor event based sampling or precise event based sampling?
According to section 17.4.9 of Volume 3 of the Intel Architectures SW Developer's Manual (document 325384-071), PEBS stands for "Processor Event-Based Sampling".
The word "precise" refers a subset of performance counter events that are capable of triggering a performance monitor overflow interrupt in such a way that it is guaranteed that software can identify the specific instruction causing the overflow.
Section 17.4.9 also says, "Prior to processors based on the Goldmont architecture, PEBS facility only supports a subset of implementation-specific precise events." Looking through the various sections of Chapter 18 (describing performance monitoring support by processor family), it is clear that performance monitoring events can be split into four categories, with slightly different splits for different processor families:
- Event is not precise and Event is not supported by PEBS
- Event is not precise and Event is supported by PEBS
- Event is precise and Event is not supported by PEBS
- Event is precise and Event is supported by PEBS
It's worth noting that PEBS used to stand for "precise event-based sampling" in the Intel SDM before Goldmont. When the SDM was updated for Goldmont in 2016, it was changed to "processor event-based sampling" because PEBS on Goldmont was enhanced to support all events, not just precise events, and continuing with "precise event-based sampling" could be confusing. The PEBS facility in Goldmont, Goldmont Plus, Tremont, and Ice Lake support all events, even though only a subset of the events are precise. On all earlier microarchitectures that support PEBS, PEBS supports only precise events.