I know for intel CPU families, there are PMU(Performance Monitoring Unit) and PEBS(Precise Event Based Sampling). What is the relationship between them? Per my understanding, the PMU contains PEBS, is it right?
PEBS is a feature of the PMU.
The PMU can be used in two modes:
PEBS is an extension of "sampling". The PMU is instructed to collect additional information if a sample is taken. For example, the precise instruction counter, registers or flags are recorded.
Is PCM using any heuristic to reconcile counter values in the platforms were the PMU may not count correctly the events?For instance, in SB the flops are counted multiple times on an L1 cache-miss while the pipeline is re-issueing the op-code? Can we find any more concise explanation of how these are handled by PCM?