Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

Write Combining buffers in recent CPUs

I would like to know the number of Write Combining buffers used by the most recent Core i5, i7 and Xeon CPUs from Intel. Searching for such information did not show relevant results.
I would also like to know the size of each buffer.
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Black Belt
Since Merom or Woodcrest (the first SSSE3 CPU), the approximate function of NetBurst Write Combining buffers is performed by fill buffers, so those would be more appropriate as a search term. The routing of data is very different in the usual cases, apparently motivating the change in name. As far as I know, fill buffers remain at 10 per core, still 64 bytes each, and are divided between hyperthreads on demand, rather than split evenly. Due, I suppose, to the enhanced cache coherency machinery introduced with the original Core I7, fill buffers haven't received much updated attention from the programmer point of view. Intel compilers appeared to have kept pace in evaluating the trade-off between fill buffer eviction and data locality when fusing and distributing loops, with the exception of the still remaining problem of mis-aligned read back of data from fill buffer.
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