Xeon Uncore Performance Monitoring documentation bugs

[James_M_3]

Referring to document Intel Xeon Processor E5 and E7 v3 Family Uncore Performance Monitoring

Reference Manual. Document number 331051-002, dated June 2015.

1. Some of the tables have table numbers (e.g. Table 2-20, etc). Some tables do not. This should

    be consistent. All tables should have a corresponding table number.

2. Page 52, CBO Box Common Metrics (Derived Events) table (no table number).

    The equation for IO_READ_BW is documented as:

     (TOR_INSERTS.OPCODE

     with: { Cn_MSR_PMON_BOX_FILTER0.tid=0x3E, Cn_MSR_PMON_BOX_FILTER1.opc=0x1C8} +

     TOR_INSERTS.OPCODE

     with: Cn_MSR_PMON_BOX_FILTER.opc=0x1E6) * 64 / 1000000

    Issues: A reference to Cn_MSR_PMON_BOX_FILTER is a bug. Each coherency domain contains

    two filter registers, FILTER0 and FILTER1 (Table 2-13 CBo Performance Monitoring Registers).

    There is no reference to FILTER. Programming these registers is precise work, and the documentation

    should contain the commensurate level of correctness and precision. Do not use FILTER - be specific,

    either FILTER0 or FILTER1.

    Second issue. There is an inherent implication that both FILTER0 and FILTER1 contain an OPC (opcode)

    field. This is not the case. Only FILTER1 contains an opcode field (bits 28:20) - FILTER0 does not

    contain an opcode field. 

    This makes the documented equation for IO_READ_BW confusing and incorrect, because the doc

    indicates an opcode should be set in both FILTER0 and FILTER1 registers, but, as just stated,

    according to Table 2-18 CnMSR_PMON_BOX_FILTER0 Register Field Definitions, the FILTER0

    register does not contain an opcode field.

    Note the same problem exists in the equation for IO_WRITE_BW.

    Note also for the LLC_DRD_MISS_PCT, again the equation explicitly references FILTER and FILTER0.

    What should the reader assume “FILTER” is? FILTER0 or FILTER1? There again is an implicit

    reference that both FILTER registers contain a state field. They do not. FILTER0 23:17 is a state

    field. FILTER1 does not contain a state field.

Thanks and best regards

Jim

[James_M_3]

Also, for IO_READ_BW, the documentation's equation showing Cn_MSR_PMON_BOX_FILTER1.opc=0x1c8 seems to be another bug.

Opcode 0x1c8 is described in table 2-20 as Request Invalidate Line - Request Exclusive Ownership Of a Cache Line.

I suspect this is supposed to be opcode 0x19c, PCIe Write (allocating).

Note this same bug exists in the v4 family (broadwell) document as well.

Best

Jim