I am new to this development thing. I am working on Hardware Performace Counter. I had some very basic questions for my understanding.
1. Are HPC specific to each core or are shared among different cores?
2. Where are they located?
3. If specific to each core, what type of data perf is providing?
Welcome to the exciting world of hardware performance counters. There are counters that count events are specific to a core (e.g. the number of instructions retired, or the number of mispredicted branches) and there are "uncore" counters that can count events like data transfers in the memory controller. Depending on what they are counting, the counters are located in the core or in the uncore respectively. The supported events depend on the processor architecture that you are using. You can find a list of events at https://download.01.org/perfmon/index/
As Thomas mentioned, there are hardware performance counters in a number of different units of the processor, differentiated by the mechanism(s) used for accessing the counters.
The phrase "performance counters" most commonly refers to the performance counters in the cores. The infrastructure for these counters is described in Chapter 18 of Volume 3 of the Intel Architectures Software Developer's Manual (Intel document 325384 -- the most recent revision is 066, published in March 2018). The events that can be counted are mostly different on different processor models -- Chapter 19 of the same document briefly describes the events for each model. When HyperThreading is enabled, these counters typically only increment for events pertaining to the specific Logical Processor that is reading the counter. Exceptions are noted in the event descriptions in Chapter 19.
The details vary by processor model, but the core performance counters typically include events related to