Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

iMC bypass commands

midhul
Beginner
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Hello,

 

I am trying to measure iMC performance monitoring counters on a Cascake Lake server. In particular, I am looking at the number of DRAM Activate commands issued by the iMC on a per-channel basis (ACT_COUNT event in section 2.3.7 of Intel Uncore performance monitoring manual: https://kib.kiev.ua/x86docs/Intel/PerfMon/336274-001.pdf)

 

The ACT_COUNT event has 3 filters (3 umasks):

  • ACT_COUNT.RD: "Activate due to Read"
  • ACT_COUNT.WR: "Activate due to Write"
  • ACT_COUNT.BYP: "Activate due to Bypass"

When I run a simple benchmark performing reads of random cache lines on a single core, a significant fraction of activates (~75%) are of the third type (ACT_COUNT.BYP).  I am trying to understand what the third type of activates (ACT_COUNT.BYP) refers to. What is "Bypass"? I see another relevant counter "BYP_CMDS" (Bypass command events), and the description says "ACT command issued by 2 cycle bypass". Does anyone know what this 2 cycle bypass means, and how these are different from normal activates? I had no luck finding anything pertaining to "bypass" in the DRAM literature.

 

Thanks

Midhul

 

 

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A_T_Intel
Employee
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There is an optimized path in the memory controller that may be taken by qualifying reads to reduce latency and these will count as ACT_COUNT.BYP. This only applies to reads, so to get the total read activates you will need ACT_COUNT.BYP + ACT_COUNT.RD.

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