locking code and data in L1/L2 cache.

Software Tuning, Performance Optimization & Platform Monitoring

Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

locking code and data in L1/L2 cache.

228 Views

anyone can provide with sample code in ASM64, for locking code and data in L1/L2? I am an ARM guy transitioning to Intel architecture. my code will run on xeon e3-1240v3. tnx much.

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.