locking code and data in L1/L2 cache.

Software Tuning, Performance Optimization & Platform Monitoring

Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.

locking code and data in L1/L2 cache.

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anyone can provide with sample code in ASM64, for locking code and data in L1/L2? I am an ARM guy transitioning to Intel architecture. my code will run on xeon e3-1240v3. tnx much.

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