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Aleksandr_B_
Beginner
102 Views

memory bandwidth on core i3 (Westmere/Clarkdale)

I'm trying to measure memory bandwidth on Core i3 530 CPU with pcm.exe and pcm-memory.exe utilities (v.2.9) but seems it's impossible. Here are what I got:

from pcm.exe:

-----------------------------------------------------

DEBUG: Setting Ctrl+C done.

 Intel(r) Performance Counter Monitor V2.9 (2015-08-07 10:23:17 +0200 ID=721d9e3)

 Copyright (c) 2009-2015 Intel Corporation

Starting MSR service failed with error 2 Trying to load winring0.dll/winring0.sys driver...
Using winring0.dll/winring0.sys driver.

Number of physical cores: 2
Number of logical cores: 4
Number of online logical cores: 4
Threads (logical cores) per physical core: 2
Num sockets: 1
Physical cores per socket: 2
Core PMU (perfmon) version: 3
Number of core PMU generic (programmable) counters: 4
Width of generic (programmable) counters: 48 bits
Number of core PMU fixed counters: 3
Width of fixed counters: 48 bits
Nominal core frequency: 2933333326 Hz

Detected Intel(R) Core(TM) i3 CPU 530 @ 2.93GHz "Intel(r) microarchitecture codename Westmere/Clarkdale"
DEBUG: caught signal to interrupt: Ctrl-C event
Cleaning up

 Zeroed PMU registers

 EXEC  : instructions per nominal CPU cycle
 IPC   : instructions per CPU cycle
 FREQ  : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
 AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state'  (includes Intel Turbo Boost)
 L3MISS: L3 cache misses
 L2MISS: L2 cache misses (including other core's L2 cache *hits*)
 L3HIT : L3 cache hit ratio (0.00-1.00)
 L2HIT : L2 cache hit ratio (0.00-1.00)
 L3MPI : number of L3 cache misses per instruction
 L2MPI : number of L2 cache misses per instruction
 READ  : bytes read from memory controller (in GBytes)
 WRITE : bytes written to memory controller (in GBytes)
 TEMP  : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature


 Core (SKT) | EXEC | IPC  | FREQ  | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3MPI | L2MPI |  READ | WRITE | TEMP

   0    0     0.09   0.72   0.12    0.50     249 K    946 K    0.74    0.39    0.00    0.00     N/A     N/A     64
   1    0     0.00   0.25   0.00    0.46    4784       19 K    0.76    0.24    0.00    0.01     N/A     N/A     64
   2    0     0.11   0.80   0.13    0.50     244 K   1096 K    0.78    0.36    0.00    0.00     N/A     N/A     53
   3    0     0.00   0.29   0.00    0.46    3927       19 K    0.80    0.24    0.00    0.01     N/A     N/A     53
-----------------------------------------------------------------------------------------------------------------------------
 SKT    0     0.05   0.75   0.07    0.50     502 K   2082 K    0.76    0.37    0.00    0.00 N/A     N/A     N/A
-----------------------------------------------------------------------------------------------------------------------------
 TOTAL  *     0.05   0.75   0.07    0.50     502 K   2082 K    0.76    0.37    0.00    0.00     N/A     N/A     N/A

 Instructions retired:  575 M ; Active cycles:  768 M ; Time (TSC): 2943 Mticks ; C0 (active,non-halted) core residency: 13.14 %

 C1 core residency: 71.99 %; C3 core residency: 14.87 %; C6 core residency: 0.00 %;
 C3 package residency: 0.65 %; C6 package residency: 0.00 %; C7 package residency: 0.00 %;

 PHYSICAL CORE IPC                 : 1.50 => corresponds to 37.47 % utilization for cores in active state
 Instructions per nominal CPU cycle: 0.10 => corresponds to 2.44 % core utilization over time interval
----------------------------------------------------------------------------------------------

          package/CPU energy (Joules)  DIMM energy (Joules)
----------------------------------------------------------------------------------------------
 SKT    0            N/A                      N/A   
----------------------------------------------------------------------------------------------


as you can see Read/Write fields are N/A.

from pcm-memory:

DEBUG: Setting Ctrl+C done.

 Intel(r) Performance Counter Monitor: Memory Bandwidth Monitoring Utility V2.9 (2015-08-07 10:23:17 +0200 ID=721d9e3)

 Copyright (c) 2009-2015 Intel Corporation
 This utility measures memory bandwidth per channel or per DIMM rank in real-time

Starting MSR service failed with error 2 Trying to load winring0.dll/winring0.sys driver...
Using winring0.dll/winring0.sys driver.

Number of physical cores: 2
Number of logical cores: 4
Number of online logical cores: 4
Threads (logical cores) per physical core: 2
Num sockets: 1
Physical cores per socket: 2
Core PMU (perfmon) version: 3
Number of core PMU generic (programmable) counters: 4
Width of generic (programmable) counters: 48 bits
Number of core PMU fixed counters: 3
Width of fixed counters: 48 bits
Nominal core frequency: 2933333326 Hz
Access to Intel(r) Performance Counter Monitor has denied (no MSR or PCI CFG space access).
Cleaning up

----------------------------------------------------

I ran it as Admin on Windows 7 x64. Please advise.

0 Kudos
3 Replies
Thomas_W_Intel
Employee
102 Views

Alexandr,

unfortunately, uncore metrics like memory bandwidth are only supported on 2nd generation Core architecture onwards. Only for those architectures, it is documented how to monitor the memory controller.

Kind regards

Thomas

 

 

Aleksandr_B_
Beginner
102 Views

Thomas, thank you for clarification.

Fang7
Beginner
102 Views

I wonder where I can download specification manual /datasheets etc/ core i3 (Westmere) ?

Reply