Software Tuning, Performance Optimization & Platform Monitoring
Discussion around monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform monitoring

pqos and CHAs

aozcan
New Contributor I
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Hi,

 

Is it possible to modify memory address - CHA affinity via:

 

https://www.mankier.com/8/pqos

 

It sounds like this might be possible. If that would be the case, how would pseudorandom Intel hashing function that maps memory addresses to CHAs would change (if it changes at all)?

 

Thanks and best regards

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McCalpinJohn
Black Belt
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As far as I know, all of Intel's cache allocation control technologies work by restricting the number of "ways" of the cache that can be accessed for a particular QoS class or access type.  For example, DMA writes to system memory are cached in 1 or 2 "ways" of the LLC.  The mapping of address to CHA slice and to set within the CHA is unchanged, but the cache is effectively direct-mapped or 2-way set associative for those transactions. 

Section 17.19.2 of Volume 3 of the Intel Architectures SW Developer's Manual supports this general understanding of how Intel's Cache Allocation Technology works, but notes that the implementation may differ from a simple 1:1 mapping:

It is generally expected that in way-based implementations, one capacity mask bit corresponds to some number of ways in cache, but the specific mapping is implementation-dependent.

 

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