We are using an embedded COM Express™ Intel® Core™ i7 Celeron processor with an Intel® 5 Series HM55 chipset by Congatec, model conga-BM57.
We have on our carrier also an Altera™ Startix IV FPGA.
We have (in this Hardware design) one ATX Power supply with no ability to turn it on selectively (ON=all voltages are ON).
We are facing a PCIe "no communication" problem (We can see it only when the Windows OS finishes to start up) one of 7-10 "power-on" cycles to the system
We saw that if we wait three seconds - till the FPGA reports "I'm ready" - before setting the "PWR_OK" signal, the BIOS sometimes doesn't start.
On the other hand, if we set no delay before the PWR_OK except waiting (100-500msec) that the Power Supply reports "Power_Good", we get the PCIe no-comm situation most of the times - but the BIOS always starts.
We tried to:
1. Add a 1.5-2sec delay before setting the "PWR_OK", letting the FPGA "some more time" to get ready.
2. Adding a "SYS_RESET#" use by setting the signal '1'>'0'>'1' for 50msec. First we set it when the FPGA reports "I'm ready" (It happens approx. 3sec from the Power_Supply "PSON#" set).
Later we set it 1 sec after he FPGA reports "I'm ready".
These to changes brought us to approx. 1 "PCIe no-comm situation" for 50 start-ups of the system.
Another important thing is, if we "restart" Windows (The Power Supply and the system stay ON), it starts up with everything OK - The PCIe works stable. We did also "stress" tests to the PCIe comm successfully.
In order to bring the system to 100% successful start-ups and no problems with PCIe. May I ask for any guidelines for the Power-Up Sequence and/or using the PWR_OK and the SYS_RESET#?
What is the typical timing for the SYS_RESET#? What is the maximum period of time that a delay before PWR_OK can be set safely?