DDR or DDR2 SDRAM controller

[Altera_Forum]

I builded a DDR or DDR2 SDRAM controller using QuartusII MegaWizard Plug-In, ip toolbench. It should have self-testing function. But I can not run it in QuartusII's simulation. No DDR address, data and control signal output from top level module. 

 Who have used altera's DDR or DDR2 SDRAM controller's IP?  Thanks  Nick

[Altera_Forum]

The simulation models are operational with ModelSim (using the optional simulation models to replace encrypted IP code). If part of it would run with Quartus simulator, you wouldn't get much information from it, cause you can't connect a RAM simulation model in Quartus. Without a model, the controller can't perform calibration phase. Although the DDR controller generally can be simulated in ModelSim, it's a rather longwinded, time consuming process. You need some patience to advance to operation phase in simulation run.

[Altera_Forum]

Dear FvM, 

 Thank you very much.  I will simulate DDR controller with ModelSim.  Thanks  Nick

[Altera_Forum]

When I simulate DDR controller with ModelSim, I met the follows error. 

 after source ddr2_ddr_sdram_vsim.tcl  # ** Error: (vsim-3033) ../../ddr2.v(176): Instantiation of 'ddr2_auk_ddr_sdram' failed. The design unit was not found. # Region: /ddr2test_tb/dut/ddr2_ddr_sdram # Searched libraries: # C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/sgate # C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/220model # C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/altera_mf # C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/stratixii   Then I complied 'ddr2_auk_ddr_sdram' in library auk_ddr_user_lib,  after source ddr2_ddr_sdram_vsim.tcl  # ** Error: (vsim-3033) D:/work/4xHD/DDR2/ddr2_auk_ddr_sdram.v(259): Instantiation of 'auk_ddr_controller' failed. The design unit was not found. # Region: /ddr2test_tb/dut/ddr2_ddr_sdram/ddr2_auk_ddr_sdram_inst # Searched libraries: # C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/sgate # C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/220model # C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/altera_mf # C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/stratixii    At last, I can not find 'auk_ddr_controller' code because it is altera's IP library. How can I do simulation?

[Altera_Forum]

I have resolved the problem.  

 Using the optional simulation models to replace encrypted IP code,  I can run the simulation.

[Altera_Forum]

what is the optional simulation models and how to replace encrypted IP code. 

thanks for your help.

[Altera_Forum]

replace the encrypted IP code with the gate level file "*.vo".

[Altera_Forum]

how to get the gate level file "*.vo" 

 my modelsim display: ** Error: (vsim-3033) E:/FPGA/video_delay/ddr2_auk_ddr_sdram.v(249): Instantiation of 'auk_ddr_controller' failed. The design unit was not found. then I add the auk_ddr_controller.vhd(the file in the ip folder) to the work.  modelsim display : ** Error: F:/altera/72/ip/ddr_ddr2_sdram/lib/auk_ddr_controller.vhd(1): expecting: ARCHITECTURE CONFIGURATION ENTITY LIBRARY PACKAGE USE thank you very much

[Altera_Forum]

use Altera MegaCore IP Library to generate "*.vo".

[Altera_Forum]

thanks for your help

[Altera_Forum]

I come back. :) 

i add the ddr.vo to the work and simulate ,modelsim display:   ** Error: (vsim-3033) E:/FPGA/video_delay/ddr2.vo(29703): Instantiation of 'oper_add' failed. The design unit was not found. why? I miss a lib?

[Altera_Forum]

thank you sz_yxf. 

I have resolved the problem.  now my simulation is OK,Because I miss two libs named sgat and 220model. thank you very much