I am using a DE0 Nano, which has a 50MHz clock. In Quartus, this clock is the input to a PLL which has an output clock frequency of 1000MHz. This compiles. The clock is input to Verilog code that sends an alternating 1 and 0 bit to a GPIO pin on the clock's rising edge. When I examine the voltage output on the scope I get a square wave with a frequency of 375kHz. Why is this?
How can I ensure that the output on the GPIO has the same frequency as my PLL clock?
If this is a hardware issue, what is an Altera board that has GPIO pins that can support voltage frequencies at 200MHz or above? The higher the better.
Here is my Verilog Code:
module code(input clock, output reg sig);
`define PKTLEN 8
localparam PKTLEN = `PKTLEN;
reg [0:PKTLEN-1] mag = `PKTLEN 'b10101010;
reg [31:0] i = 0;
always@(posedge clock)
begin
sig = mag[i];
if (i < PKTLEN-1) begin
i = i+1;
end else begin
i=0;
end
end
endmodule
