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Altera_Forum
Honored Contributor I
915 Views

Issue with scfifo when clear is active

Hi, 

 

I am expecting output of fifo (which is qsys generated and uses scfifo) to be zero when clear is active but its giving unknown. 

The partial code of scfifo for clear signal is given below which is in file altera_mf.v 

 

always @(posedge clock or posedge aclr) 

begin  

if (aclr) 

begin 

if (add_ram_output_register == "ON") 

tmp_q <= {lpm_width{1'b0}}; 

else if ((lpm_showahead == "ON") && (use_eab == "ON")) 

begin 

tmp_q <= {lpm_width{1'bX}}; 

end 

else 

begin 

if (!stratix_family) 

begin 

tmp_q <= {lpm_width{1'b0}}; 

end 

else 

tmp_q <= {lpm_width{1'bX}}; 

end 

 

 

It's taking stratix_family value as 1. So the last line tmp_q <= {lpm_width{1'bX}} is getting excersized. 

 

And the expression for stratix_family in scfifo is as follows. 

stratix_family = (dev.FEATURE_FAMILY_STRATIX(intended_device_family));  

 

The device chosen is of arria 10. So it's taking intended_device_family as arria 10. I checked the function FEATURE_FAMILY_STRATIX which is in altera_mf.v to debug. But not getting why stratix_family is assigned with value 1. Please help out. Thank you. 

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4 Replies
Altera_Forum
Honored Contributor I
56 Views

Either way, you shouldnt be using the output of a FIFO when clear is active. The data is only valid when empty = '0'

Altera_Forum
Honored Contributor I
56 Views

As output of FIFO is driving something, I am not supposed to have unknown even when clear is active.  

So I am expecting output of FIFO to be zero when clear is active.
Altera_Forum
Honored Contributor I
56 Views

What are you driving? in the real hardware, unknown will not exist, it will be '0' or '1' in real hardware.

Altera_Forum
Honored Contributor I
56 Views

 

--- Quote Start ---  

As output of FIFO is driving something, I am not supposed to have unknown even when clear is active.  

So I am expecting output of FIFO to be zero when clear is active. 

--- Quote End ---  

 

Then you will need to change your expectations to match what the component actually does. Possibly, you have the FIFO configured to output data prior to being read in which case, since nothing has been put in yet, unknowns are the output. Or maybe the clock isn't running. 

 

In any case, the data output of any FIFO is only valid under certain conditions which depend on how the FIFO is configured to provide output data. Since you have downstream stuff that uses the data but does not factor in the data valid conditions, then you have a design issue to fix. That issue will not have anything to do with what the data outputs of the FIFO do when they are being reset. 

 

Kevin Jennings
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