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Altera_Forum
Honored Contributor I
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altera GPIOip could be inferred on VHDL on Verilog instead of generated from ip ?

Hi to all, in the user guide I did't find any possibility to infer the altera_gpio ip in the rtl code (both VHDL or Verilog), it is possible? or the ip should be generate every time for specifical use (for example DDR GPIO, LVDS GPIO, bidir GPIO and so on... ) 

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