Inserting SignalTap without re-routing design

[Altera_Forum]

I need to examine some internal signals in an existing FPGA design that was not set up for incremental compile (no design partitions specified for incremental compile). Is there a way to add a signal tap .stp file to the project and capture some post-fit signals while maintaining the existing placement and routing given that the project is not currently set up for incremental compile? Does smart compilation work for this or will it recompile the design and re-run place-&-route on everything? 

Regards, GMM

[Altera_Forum]

Smart Recompile just skips modules if they're unnecessary. It's not very useful. 

You always have a partition called Top, so just set that to Post-Fit. By default, Signal-Tap is put into its own partition and therefore won't affect Top. You need to tap post-fit nodes though. (Also, if you're able to try Rapid Recompile, that is supposed to work in this case too, preserving as much of the design as it can)

[Altera_Forum]

Ok, thanks for the response. I tried creating post-fit partition on Top, but when I compiled, I got a message warning that the previously generated Fitter netlist for partition "Top" does not exist. I believe it then used the previously generated synthesis netlist. After the recompile (that ran place & route again which I was hoping to avoid), subsequent compiles after that did recognize the "Top" post-fit netlist and didn't place & route again. I guess the post-fit netlist with full incremental compile enabled needs to have been generated before it will avoid doing place and route again. If adding a SignalTap .stp file to the project at this point, I'm assuming Incremental Compilation needs to be enabled (checked) for the SignalTap instance, but I'm confused as to how this relates to the incremental compile done for the partitions. Does this mean the routes & memories added for signalTap will be unchanged assuming nothng in the .stp file has changed from the last compile?

[Altera_Forum]

Hmm. You should have a Partition called Top automatically, and after compiling a post-fit netlist already exists for it. (I assume Incremental Compilation is on, but it's on by default and you'd have to go out out of your way to turn it off.). Then just set that Top Partition to Post-Fit, add your signaltap, which again is automatically a partition although it won't show up as one in the Partitions Window, but you will see it in the Incremental Compilation sections of the output reports.

[Altera_Forum]

--- Quote Start ---  Hmm. You should have a Partition called Top automatically, and after compiling a post-fit netlist already exists for it. (I assume Incremental Compilation is on, but it's on by default and you'd have to go out out of your way to turn it off.). Then just set that Top Partition to Post-Fit, add your signaltap, which again is automatically a partition although it won't show up as one in the Partitions Window, but you will see it in the Incremental Compilation sections of the output reports.  --- Quote End ---    I believe the problem is the original design settings had incremental compile turned off. I am having to use an old tool version (Quartus 6.0) due to presence of Nios & avalon switch fabric in the design (from past painful experience, I avoided upgrading to a newer tool), so maybe the default is off for that version or the original designer turned it off.

[Altera_Forum]

Hi 

 I am working on an FPGA project in which the behavior of the design changes as soon as I add signal tap to it.   I have a design with some bugs that I am trying to debug. But whenever I tap out signals, I am unable to recreate the issue and I see something very different from what I was seeing without signal tap.  I am using Quartus 15.0.1. Can someone please explain to me the process of preserving the design while adding signal tap.  Thanks

[Altera_Forum]

Your top-level is in a partition automatically, so: 

1) Make a copy of the design that has the problem, including /db and /incremental_db. (Basically copy the directory with the .qpf/.qsf in it and all sub-directories) 2) Assignments -> Design Partition Window to open it 3) Set the Top partition(and any you might have created) to Post-Fit. If you want, you can right click on them and go to Partition Properties and click the option to Ignore Changes in Source Files, in which case they will always be Post-Fit even if you change your source, but this shouldn't be necessary. 4) Add SignalTap, and be sure to only tap SignalTap: Post Fit nodes. The main thing to look for is registers, as they should be kept and have a name that makes sense. 5) Compile. SignalTap is its own partition, so it will get synthesized independently and then placed-and-routed around your post-fit partition/s. 6) Modify SignalTap and repeat until you find the problem. 7) Be sure to set the partition back to Source or Post-Synthesis and uncheck Ignore Changes in Source if you had checked that.

[Altera_Forum]

Hi 

 Thanks for your reply Rysc. I followed your steps and I am still having the same problem.  My board sits between the host and server and modifies the packets that are exchanged between them. In my original design I am able to set up a tcp connection between the host and server. I have a bug which occurs in application packets that are sent after connection establishment. With signal tap added, I am not even able to establish a tcp connection.  I have some timing failures at 85 and 0 degrees slow corners that I am trying to fix. Could that be the reason for this erratic behavior?

[Altera_Forum]

In the fitter report, if you go to Incremental Compilation, was your design's placement and routing preserved?

[Altera_Forum]

Hi 

 No there is 0% requested and achieved for both placement and routing.  I have followed your steps and checked by compiling twice.  Could I be doing something wrong? What is the solution?

[Altera_Forum]

Something is going wrong, but hard to say. Synthesis and Partition Merge(if it runs) both have reports about Incremental Compilation and might give a clue. For example, analysis and synthesis might say that the design files have changed and resynthesizing, in which case the post-fit wouldn't try to lock anything down.

[Altera_Forum]

Hi Rysc 

 So I finally got signal tap in a separate partition. Basically it required 3 compilations. Here is what I did.  Compile 1: I had compiled the design and decided to tap it for debugging.  Compile 2: I created a partition for my design.  In Project Navigator window I clicked on Hierarchy tab. Selected the module that I wanted to preserve. Right clicked on it and selected Design Partition-->Set as Design Partition. Now I could see my module in Design Partition Window. I changed its Netlist type to Post-Fit.  Compile 3: Now I added a signal tap to the project.  I can see the design being preserved in the reports now.  Question Is it possible to view Pre-synthesis nodes in signal tap using this method (Im trying it out right now)? The signals that I want to see are not visible in Post fit mode.  Thanks for your help

[Altera_Forum]

You shouldn't have to do Compile 2. Note that your design is in a partition called Top automatically, so as long as you don't mind preserving the entire design(besides SignalTap, which is automatically not preserved), then just set that Top to Post-Fit. 

When you do create a partition, your entire design has to be resynthesized and refit from scratch, so you can't preserve the stuff from Compile 1. Remember that a partition is synthesized independently of other partitions, and by doing so, it's placement info can be preserved. When you create a new partition in Compile 2, the partition information in Top changes too, so that has to be resynthesized and refit as well as your new partition. Skipping Compile 2 and just setting Top to Post-Fit will preserve everything and should work. As for looking at pre-synthesis nodes, the answer is no, not if you want to preserve placement and routing. Those presynthesis nodes generally don't exist anymore. Think of a 2 input AND gate feeding a 3 input OR gate in your RTL. After synthesis, these may all be merged into a single LUT. If you want to tap the output of the AND gate, it doesn't exist anymore and the only way to get at it is to go back and resynthesize the design so the AND gate is the output of a LUT, but if you resynthesize then the node names change(and changes in one area of synthesis can affect other areas) so the post-fit information no longer applies.

[Altera_Forum]

I think I know what the problem was. I'm using Qsys in my design and as a first step I generate my design files. This makes it necessary for me to set the design partition property of my Top partition to Ignore source files changes. 

 Once I did this I could get signal tap to work. But not every time. During the routing stage, my fitter attempts to route a few times and then it fails. I have confirmed this by compiling the design with no/just one signal in my .stp file versus a bunch of signals. It works in the former case but not in the latter.  Please see the attachment for log messages. Is there a work around for this?  thanks

[Altera_Forum]

Sorry, not sure. I haven't seen that before. Since one of the partitions is locked down it is possible to have something that is just impossible, although looking at your routing utilization it doesn't look bad at all. Maybe tapping other nodes will get around it or provide enough information to proceed? 

 One other idea is to follow the same flow but do Rapid Recompile, if it's available. It depends on version of Quartus, device, etc. Check under Processing -> Start -> Rapid Recompile.