I am using a 1port single clcok ram from the megawizard plugin for a single cycle processor design.
when i synthesize the design quartus(6.1) is throwing an error
Error: M4K memory block WYSIWYG primitive "altsyncram:altsyncram_component|altsyncram_i2h1:auto_generated|altsyncram_fhc2:altsyncram1|ram_block3a32" utilizes the dual-port dual-clock mode. However, this mode is not supported in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature. File: /home/ecegrid/a/ece437l.old/Proj32/._dumbram/db/altsyncram_fhc2.tdf Line: 1054
but quartus (6.1) also throws this error when i synthesize the ram block by itself.
i am using the de2 development board. ep2c35f672c6 cyclone ii fpga
I am most definately not using it as a dual port dual clock ram.
any help would be appreciated.
-Eric
