Input Ports don´t show up in Timequest

[Altera_Forum]

Hi, 

I am having a very strange problem in Timequest. I want to define the clocks of my design in Quartus but when I click on target and then filter for * "get_ports", I get a list of all the ports but I do not see any input ports, only bidirectional ports and output ports.   The same happens if I try to place any constraint (e.g. set_input_delay, no inputs ports can be found)   This is really confusing me, as I recently used timequest for a different project using the same version of Quartus but without any problems. I don´t think I have done anything differently this time. I am using Quartus V9 sp1.    I would be very grateful if someone could shed some light on this for me.   Many Thanks

[Altera_Forum]

You're doing it right, and sounds like you know you're doing it right. I would guess the input ports you're looking for have been synthesized out. Try running Report Datasheet and see if they're listed there. Then go to the Technology Map View and look for them there, and if they exist, look for what they drive. But

[Altera_Forum]

Thanks Rysc for the reply, yeah looks like there are getting synthesized out. I placed some logic and attached a clock to it and it now appears in the list.  

I didn´t see any messages in the processing window of Quartus saying it was doing this. I ran a few tests on another program I had using timequest and the input pins I checked that were not used in the design were still available.    I´m not sure what critera Quartus uses to remove the input pins from the design, but anyway it seems in this case there is no serious problem.