stop inferred RAM

Altera_Forum · ‎07-17-2009

I hope someone can help, I am not too familiar with verilog and and trying to edit and SOPC component to stop it using M4K blocks and instead use registers.

Is there a way to stop Quartus inferring RAM nodes?

Below is the bit of code.

module raminfr   
        (clk, we, a, dpra, di, dpo); 
parameter addr_width = 4;
parameter data_width = 8;
parameter depth = 16;
input clk;   
input we;   
input   a;   
input   dpra;   
input   di;   
output  dpo;   
reg     ram ; 
wire  dpo;
wire   di;   
wire   a;   
wire   dpra;   
 
  always @(posedge clk) begin   
    if (we)   
      ram <= di;   
  end   
  assign dpo = ram;   
endmodule

Thanks in advance.

Richard

Altera_Forum · ‎07-17-2009

try Assignments => Settings => Analysis & Synthesis Settings => More Settings => Auto RAM Replacement to off.

though when i compiled this in Quartus it wouldn't infer a RAM due to the asynchronous read.

Altera_Forum · ‎07-17-2009

thanks, but is there a way to specify not to automatically use RAM for this bit of code. I am not sure if turning this feature off will effect other parts of my design (I am trying this now).

Richard

Altera_Forum · ‎07-17-2009

try looking at:

http://www.altera.com/literature/hb/qts/qts_qii51008.pdf

page 53

ramstyle = "logic" synthesis attribute. strangely this is not listed as one of the options in Quartus help.

Altera_Forum · ‎07-17-2009

That looks more promising. I'll go and give it a try.

Thanks for the help,

Richard

edit: works a treat!