synthesis System verilog design

[Altera_Forum]

Hi there, 

 I am a new user in Quartus II and hope that will gain some help here.  I wish to synthesis a System Verilog design using Quartus II 6.0. Do anyone have a tutorial on that? I ve tried to follow the tutorial for VHDL and it shows that my top level entity is undefined. "Error: Top-level design entity "gen_reg" is undefined". I think there must be something wrong in within the process. Hope that somebody will help me out. thanks a lot.  regards, SHL

[Altera_Forum]

Is gen_reg the name of the project you created, or is it the top-level module in your design? If the top-level module isn't the project name, you need to explicitly tell Quartus otherwise. If you go to Assignments -> Settings -> General, you can change the name of the top-level module/entity of that project. You may have to then explicitly add the files, too. (Project -> Add Files)

[Altera_Forum]

hi Rysc, 

 yes. gen_reg is my project name and also the top module name. But some how it just can not and undefined. :confused:

[Altera_Forum]

Have you explicitly added the verilog file with a gen_reg module to the project? Might it have a capital letter? (Verilog is case-sensitive). Can't think of much else. You might want to file an SR.

[Altera_Forum]

Thanks for your reply RYSC. I just wondering whether the process of synthesis a System verilog design is the same as the process for VHDL design? 

I ve tried to synthesis one of my VHDL design with the same process as the System verilog and it was successfully done. So I am wondering whether is there any other extra steps to be carrying out in synthesis System Verilog design?

[Altera_Forum]

There's no difference in the synthesis "process" in the Quartus II software - you just have to create your design files, create a Quartus II project, make sure the top-level entity/module in the code (like the top-level module) is marked in the software, add your files to the project, and compile. (Adding files is required if they are located in a different directory or if the file name does not match the entity/module name, but it's good practice to add them all so you are specifying exactly which files to use).  

 But of course the syntax is different, and the way the source code is structured (entity/architecture vs module etc.) Perhaps you don't have a top-level module that uses the name you specified as the top-level entity in the project?

[Altera_Forum]

With Quartus-II 7.1 (web-edition), I've noticed that if you have *any* coding or structural errors in your RTL-files, Quartus-II sometimes produces bogus/fake error-messages. 

 For example, I had 10 Systemverilog RTL files in my design. They simulated fine in Modelsim 6.2g PE Student Edition, but nevertheless contained some non-synthesizeable coding errors. When I ran the files through Quartus-II, Quartus-II printed error messages on 2-3 files. But I checked the 2nd and 3rd files -- they looked fine. When I went back and fixed the errors in the first file, all the errors disappeared.  Xilinx's ISE sometimes does the same thing.  Anyway, getting a multi-file project to synthesize, for the first time, is a trial & error process. (Unless you had access to a real linter or formal syntax-checker -- in which case all errors should have already been caught and corrected.)

[Altera_Forum]

The Quartus top level entity must be the name of the top module not the name of its file. e.g. if the file "Lab1.v" starts with: 

"module part1 (SW, LEDR);" then the top level entity must be "part1" not "Lab1.v"! Or you can just name the top module the same as its file name to make the problem go away.