code problem

[Altera_Forum]

Hi, I am wring a mermory code, but the waveform is not correct. There is no change of fin_add, only when add_en='1' then add_en_next change. I think probable it is coz the used(num) never become zero. but I don't know this happen. my code is as folllow: 

architecture behv of mry is   signal num,match_num:integer; signal used:std_logic_vector(3 downto 0);--! type CAM is array(0 to 3) of std_logic_vector(15 downto 0); signal data_array: CAM; begin process (init,add_en,num,used)   begin  fin_init<='0';  fin_add<='0';   add_en_next<='0';      if init='1' then --init  used<=(others=>'0');   fin_init<='1';    elsif add_en='1' then ---add    for num in 0 to 3 loop  add_en_next<='1';  if used(num)='0' then ---cell is empty  add_en_next<='0';  used(num)<='1';   data_array(num)(15 downto 8)<=H_Dn;  data_array(num)(7 downto 0)<=H_GD;  fin_add<='1';  exit;  end if;  end loop;  end if;  end process;  end behv;

[Altera_Forum]

You trying to build a memory as pure combinational code (without a clock).  

This is at least not synthesizable in FPGA.

[Altera_Forum]

Thanks.  

But it is essential to use clk, any other way not by using clk?

[Altera_Forum]

I don't see another option.

[Altera_Forum]

I agree with FvM.

[Altera_Forum]

Is it a model of the asynchronous DRAM?  

 Is it only behavioural model? So you do not suppose to synthesize this architecture? Because for only behavioral check this architecture could be OK. But you should specify a delay on each gate to simulate the behaviour properly, because these ones: add_en_next<='0'; used(num)<='1';  data_array(num)(15 downto 8)<=H_Dn; data_array(num)(7 downto 0)<=H_GD;   Will happen almost simultaneously, the only difference - different delta cycles in the simulator.   If you want to synthesise this stuff, it would generate not safe latches with glitches possibility. For synthesis in FPGAs you have to use the RTL style of coding.

[Altera_Forum]

Apparently, the intended design purpose is to fill a new memory location each time add_en is asserted.  

In my opinion, it can't be done asynchronously, at least an edge detection for the add_en signal is needed.

[Altera_Forum]

caraey, 

If to tell why your code is not working, that's because you assign: fin_add<='0';  and  fin_add<='1';    in the same process.   Only the last assignment to a signal is in force. Read more about VHDL: Behavior with Processes

[Altera_Forum]

Thanks, all u guys. It is really helped. 

But uilka b, about we u said, how can I change fin_add to '0' if I cannot use it in the same process. what I worte is hope is the if is correct then fin_add to 1. otherwise, I hope the it keep in zero.

[Altera_Forum]

Yes, use variables.

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

I was just describing the situation why the "fin_add" never changes. At the beginning there is the code  

  --- Quote Start ---  process (init,add_en,num,used)  begin fin_init<='0'; fin_add<='0';  --- Quote End ---   and logically there should be a change of the fin_add after something changed in the sensivity list.    But since the process exectution enters the IF branch - fin_add<='1' and only last assignment in the process takes place. Therefore he will not notice '0' assignment on the waveform.   Thats true If his fin_add always = '1' this means that his process always enters to the branch there fin_add assigned '1'. The problem can be in the testbench.

[Altera_Forum]

Apart from the question, if the presented code as a whole has a reasonable operation (I said, why it can't in my opinion), the usage of fin_add and fin_init in the process is reasonable as such. But when the for loop iteration is translated to combinational code, these signals loose their original function. As uilka_b pointed out, they never change, respectively they are eliminated.