invalid sof? please help me...

[Altera_Forum]

Hi, 

i am close to desperation because i am completely blocked with my work. I made a simple quartus design, a bdf including a 1s10 processor, compiled it and it reported no errors, programmed it on the board via programmer. Now i go to niosIDE to program this system, but when i launch my program (which was correctly built) it says:  "There are no Nios II CPUs with debug modules available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary."  What's wrong? I asked at altera mysupport, all they said me is to not click cancel on the openCorePlus message window when i am downloading the program to the board since i have a time_limited.sof as the result of the compilation, but i don't do that. ...  :( :( :(

[Altera_Forum]

Is the chip resetting? If you have unused pins driving ground when they're not supposed to, you can trigger a over-current condition resetting your board. By default Quartus reserves all of your unused pins as "output driving ground"

[Altera_Forum]

where can i check the status of unused pins?

[Altera_Forum]

Assignment -> Settings, under the device page, click device and Pin Options. Select the appropriate option under the "Unused Pins" tab.

[Altera_Forum]

Unused pins are displayed with all other pins in fitter report. You could prevent from the said problem by setting unused pin default to input with weak-pullup or hold in device settings / "unused pins".  

 I would generally check, if the FPGA is configured with the intended design, e. g. by driving a test LED. I think, it could rather be an issue with Nios II configuration, but I can't help in this regard cause I'm not using Nios.