question of the FPGA state after different configuration process?

[Altera_Forum]

Is there any difference of the FPGA state between the power-up configuration and the reconfiguration after successful configuration ? 

Thank you!

[Altera_Forum]

The question in doubt could be, if all initialisation action, that is carried out after power-on reset is also performed with an reconfiguaration? Particularily, if power-up level, that is low internally for all FPGA registers (but may be inverted by logic), is also restored with a reconfiguration. I think that this is the case, but I didn't found it exactly stated in device handbooks, also the term power-up level may give raise to doubts.

[Altera_Forum]

thank you for your answer:)

[Altera_Forum]

All registers should go back to 0, I believe. The one thing that concerns me is memory content that hasn't been re-configured, but hopefully you're not depending on the memory locations you haven't written to. (RAMs with an initialization file will naturally be reconfigured).  

Note that it is common practice to have an asynchronous reset for every clock domain, and to release this reset after power-up. This is not to ensure the state of registers out of power-up, but to ensure that all registers are see the same first clock cycle. Otherwise you are susceptible to Recovery/Removal logic failures. (If using the Classic Timing Analyzer, you need to turn on R/R analysis under Assignments -> Settings -> Timing Analyzer -> More Settings. It's on by default in TimeQuest.) This is one of those topics most people ignore, and then have spurious power-up failures, which is why it's good practice to do this right from the get-go.