JTAG BST Cyclone III

[Altera_Forum]

Hi, 

 Can anyone help understand this condition for nconfig "The IEEE Std 1149.1 BST circuitry for these Altera devices are dedicated and enabled upon device power-up. You can use this IEEE Std. 1149.1 BST circuitry both before and after device programming or configuration. However, the nCONFIG pin on the FPGA families must be held low when you perform JTAG boundary-scan testing before configuration."  In our design nconfig is pulled-up, we use FPP mode for the configuration. Is there another way to do the BST without configuring the FPGA and keeping nconfig pulled high?  Please help :confused:  Thanks MJ

[Altera_Forum]

The same condition can be found in any other Altera FPGA manual. I'm not sure, what it means in detail, particularly which BST functions are possibly unavailable when not pulling N_CONGIG low. However, why don't you simply consider to load an empty configuration at begin of the boundary scan test via JTAG? Furthermore, the boundary scan test behaviour is partly modified by the actual I/O configuration. You may want to set a particularly configuration during test anyway.

[Altera_Forum]

We did actually run into this issue with Cyclone II. I can tell you that the user manual is indeed correct. Fortunately we new about this ahead of time and connected the nConfig pin to our BST header so we could drive it low. 

 The other alternative we had considered is the suggestion FvM is giving. Load a useles/harmless FPGA image into the device, then run your BST.  Jake

[Altera_Forum]

Thank you for your help!