DDR interface that spans multiple sides of the device

Altera_Forum · ‎03-12-2007

I recently wanted to create a 144-bit DDR2 interface that would span across the top and bottom of a Stratix II device. The Altera MegaWizard allows you to do this but that probably isn't the best way to go. You may run into timing problems within the controller since it has to feed logic on opposite sides of the device.

Instead, build two 72-bit controllers and share the PLLs to minimize resources used. Send both the same commands, but only half of your total local data to each. Since the DDR/DDR2 controller IP core is deterministic, if you put two cores in parallel and fed them the same commands they will execute them at the same point in time.

With regards to refresh, the core simply has a counter that counts down to zero. Once it hits zero it complete the command it is executing (if any) and then does the refresh. Once complete it resets the counter and off it goes again.

So in conclusion 2 cores that are parameterized in the same way, running at the same frequency and given the same commands should always stay in step with each other.

Altera_Forum · ‎03-21-2007

Wow this is great information obviously you have some experience with DDR. I implemented a DDR core in the past and had a really difficult time meeting timing. Part of the problem was that the tcl scripts were difficult to use that the megacore generated. I have read a little about the new DDR timing wizard. Will this make timing closure easier?

Altera_Forum · ‎05-25-2007

I am trying to gather info on the DDR2 IP. It sounds like in order to interface to off-the-shelf DIMM I will need both sides of a Stratix II, is that right? Also is there a limit on the size (depth) of the DIMM?

Thanks.