PCIe Dev Kit SFP interface

[Altera_Forum]

Hey all, 

I've been working with a PCIe Stratix II GX dev board that has two on-board SFP channels available as possible high speed in/outputs. So far I'm just trying to do a basic Hello World scenario with the SFP channels. I've created a transceiver block for each of them in my design using the alt2gxb megafunction and have one channel constantly transmitting 0x01, one channel constantly transmitting 0x10. On the hardware side, I connected the two SFP channels together using a male to male SFP cable. When I run signaltap on my design, though, I'm reading that channel two is constantly receiving 0x9D instead of 0x01, and channel one is constantly receiving 0xE2 instead of 0x10. I've tried transmitting different constant values, such as 0xF0 and 0x0F, and observe different constant values on the receiver end (for that case, 0x17 instead of 0x0F, 0xFD instead of 0xF0).  I'm eventually going to be doing some packet sniffing in this project, so I have my Stratix II GX set up in GIGe transceiver mode. I've successfully used the same FPGA to transmit and receive data using XAUI, so I think that my reset procedures and control signals are correct (I'm following the reset procedure detailed in page 2-188 of the S II GX handbook). My question is this then: has anyone else worked with SFP ports on a board similar to this? I'm thinking that my problem might be with the SFP interface, since so far all the setup that I've done with them has been to set the SFP_disable pins to constantly be ground. Does anyone know if there is anymore setup required to interface with the SFP ports, or does it just require transmission to be enabled and a data stream coming along the RX/TX lines?  Thanks in advance, Jordan Wills

[Altera_Forum]

hi, I also have the same dev board.  

I am currently using: Quartus II 7.1 full version with full license.  Open Core plus.   my NIOS 2 system is not functioning. It only includes nios2, JTAG UART, PIO, onchip ram and PLL to slow down the clock.   I used the hellow pio example in the nios IDE. not working.  hellow world small example, not working.  when I check run the hellow world application in Hardware, I got the following error from the IDE console:   Using cable "USB-Blaster [USB-0]", device 2, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused   do you have this problem you are using this board for nios 2 development? Thank you.

[Altera_Forum]

This is to ezhongsjm; I responded on your other post too... 

 There is a new support solution posted on Altera's web site that documents these errors. It links to a related solution that lists patches to fix a problem with the OpenCore Plus circuitry in version 7.1 and 7.1 SP1.   http://www.altera.com/support/kdb/solutions/rd07272007_849.html (http://www.altera.com/support/kdb/solutions/rd07272007_849.html)