DRAM and SRAM with Cyclone III

[Altera_Forum]

Hello all, 

 I have some general questions regarding the use of DRAM and SRAM memories with Cyclone III devices.  1) DRAM memory Do I need to connect the DRAM memory chip directly to the dedicated pins (actually DPCLK, CDPLK.. and so as documented in Handbook chapter 6) or can I use any I/Os pins?  My understand is if I don't connect the device to the dedicated pins I will have to design my own IP (vhdl controller) to control it. But if I use the dedicated pins I could use the macrocell provided by quartus/altera. Am I correct?  2) SRAM memory Since SRAM memory is easy to control, I can connect it on any others I/Os of the Cyclone III. Is there some SRAM macrocell controller provided by Altera/quartus? Do I need to write it myself?  Thank you in advance for any advice Best Regards, -Pierre

[Altera_Forum]

If the DRAM is DDR or DDR2, use the altmemphy megafunction even if you choose not to use the DDR/DDR2 SDRAM High Performance Controller MegaCore for the controller logic. If you do use the MegaCore, it will set up altmemphy automatically. 

 Even if you create the datapath yourself instead of using altmemphy, you should use the recommended pins for DQ and DQS. But it is strongly recommended that you use the free altmemphy if you are using a memory type supported by that megafunction.  I don't know anything about the particular pins you mentioned (and I didn't try to look it up).

[Altera_Forum]

If you are using SOPC Builder, it might provide the kind of SRAM interface you need.

[Altera_Forum]

Thank you for your quick help. I continue to investigate to check if can use any I/Os or if I must use the dedicated pins. 

 If someone has already designed a digital board with Cyclone (II or III whatever) using a DRAM device, please let me know.

[Altera_Forum]

--- Quote Start ---  Thank you for your quick help. I continue to investigate to check if can use any I/Os or if I must use the dedicated pins.  If someone has already designed a digital board with Cyclone (II or III whatever) using a DRAM device, please let me know.  --- Quote End ---     Hello.  I did. I connected two DDR SDRAM to CYCLONE III (EP3C25) and everything is working. I don't use altmemphy because I need burst length equal to 8 and altmemphy doesn't support it.

[Altera_Forum]

Hello Webmoon, 

 Thank you for your answer. Is it possible to send me your Pinout or the part of your schematic with the DRAMs and the Cyclone III. I would really appreciate. Did you use the dedicated pins for the strobe signals?  Regards -Pierre

[Altera_Forum]

--- Quote Start ---  Hello Webmoon,  Thank you for your answer. Is it possible to send me your Pinout or the part of your schematic with the DRAMs and the Cyclone III. I would really appreciate. Did you use the dedicated pins for the strobe signals?  Regards -Pierre  --- Quote End ---    I used DQ and DQS pins according to ALTERA's http://www.altera.com/literature/dp/cyclone3/ep3c25.pdf (http://www.altera.com/literature/dp/cyclone3/ep3c25.pdf) PIN-OUT file.  Before making PCB board run analysis and synthesis in Quartus to make sure your project is working. Because you can see if Quartus can place some pins and don't forget to assign pins according to standart SSTL-2 Class I if you use DDR SDRAM and don't forget to connect VREF pin of CYCLONE III to 1/2 of 2.5V if CYCLONE III bank is used for DQ and DQS pins.

[Altera_Forum]

Thank you for your answer. I have to connect only one DRAM device which should use only on DQ/DQS group. 

-Pierre

[Altera_Forum]

Hello  

i want just to know if the IP for the DDR is FREE because i think that with the MEGA Wizard function the IP has a limited time and we can't put it in the device . Also one question I want to know if I can use the CLK pins as a general purpose I/O ?because all I/O pin are used Thanks very match.

[Altera_Forum]

The altmemphy megafunction used by the DDR/DDR2 SDRAM High Performance Controller MegaCore and the data path provided by the older MegaCore are free. Only the controller logic requires a license. The license for the controllers might be included with the Quartus subscription software (not web edition). I think that was the case at one point but don't know whether it still is.

[Altera_Forum]

Thank you for your answer. So I can use the MegaCore function and release my project? 

What is the deference between the controller logic and this Mega core function?  Tanks.

[Altera_Forum]

The MegaCores include both the controller and the data path. At one time the controllers required a separately purchased license. As I said before, I don't know whether that is still the case. See the documentation for the MegaCores for more information on the controller versus the data path. I think the user guide for at least the old MegaCore (the one that does not use altmemphy) discussed this.

[Altera_Forum]

Hi all, 

 I finalized my custom Cyclone III Board and I finally chose to connect a simple SDRAM to the FPGA (instead of the DDR). My FPGA input clock is 50Mhz.  Here are my conclusions:  interface a sdram (pc66/pc100) with cyclone iii :: - SDRAM/FPGA Interface signals: you can use any standard I/Os pin of the FPGA for all interface signals between SDRAM and the FPGA except for the clock signal. - Clock signal: it is recommended (not mandatory) to use a FPGA PLL output for the clock signal. By using a PLL you can easily configure the clock frequency (100Mhz for a SDRAM PC100 in my case). - FPGA IP NiosII controller: use the standard SDRAM controller provided by Altera from sopc builder. If you choose to use your SDRAM to 100Mhz (PC100) you need to do these 3 steps:  1) Instantiate a PLL to 100Mhz (with output C1 for instance), input clock is 50Mhz in my case.  2) Instantiate a SDRAM controller with sopc builder and don't forget to select PLL output as input clock for this controller (because the SDRAM controller needs to run at the same speed than the SDRAM memory chip). 3) Tunes the PLL to adjust delays betweens the 100Mhz input clock controller and the 100Mhz PLL output which is connected to the memory chip.  interface a ddr/ddr2 with cyclone iii :: I didn't connect any DDR/DDR2 chip on my board but I would do the following: 1) DQS/DQ interface signals: use the DQ/DQS dedicated pins from the FPGA 2) Other interface signals: can use any other I/OS of the FPGA 3) FPGA IP Nios controller: use the DDR/DDR2 Altmemphy controller provided by Altera.  interface a sram and a flash with cyclone iii :: - I connected a SRAM and a FLASH on the same bus to the FPGA Cyclone III. Read/Write accesses to/from these memories will be based on my 50Mhz clock. 1) Instantiate a Avalon Tristate Bridge controller and configure it 2) Instantiate a SRAM controller and configure it 3) Instantiate a Flash controller (CFI in my case) and configure it 4) Connect the 2 memories to the Avalon Tristate Bridge with sopc builder  That's all Folks, now you can Generate your NiosII system... re-compile your Quartus project with the correct pinout and... GO!  I hope this post will be useful and don't hesitate to post I you find any mistake.  Best Regards, -Pierre

[Altera_Forum]

Open quartus2. tools--megawizard plug-in manager.You can find ram memory controller there.

[Altera_Forum]

Hi Pierre, 

 Initially you asked if there are dedicated pins for the memory interface (ALTMEMPHY). The answer is yes. Please make sure you connect your ALTMEMPHY interface to the appropriate pins. You can find these pins with the Quartus II "Pin Planner" tool. Although each I/O cell for Cyclone III is pretty much the same, the dedicated pins should give the ALTMEMPHY the best performance. Quartus II should give you an error if you are using the ALTMEMPHY and do not correctly connect the pins.  You should also turn on the "Migration" feature in the "Devices & Pins" dialog box. If you plan on moving from one device to another to reduce or increase LEs/memory/etc., you want to make sure that the pin-out you are using works for multiple devices.  Hopefully this helps.  Take care, Christian