Can't Read Data from Custom componet (Avalon mm)

[Altera_Forum]

I had associated a custom component (A variation of the DCFIFO example available in AN 473) to my NIOS 2 System. I use the Avalon MM (Slave) Interface whit the current signals: 

 Readdata (32bits) out Read (Used as the component read clock) IN  Everything goes right to me, till i try to read some data from the nios 2 software. (I use the HAL, avoiding any OS)   I can find the base address in System.h #define DCFIFO_DE_TOP_0_NAME "/dev/dcfifo_de_top_0"# define DCFIFO_DE_TOP_0_TYPE "dcfifo_de_top"# define DCFIFO_DE_TOP_0_BASE 0x00400000# define DCFIFO_DE_TOP_0_SPAN 4# define DCFIFO_DE_TOP_0_TERMINATED_PORTS ""# define ALT_MODULE_CLASS_dcfifo_de_top_0 dcfifo_de_top But, when i try to read some data from the component using the IORD macro  IORD(DCFIFO_DE_TOP_0_BASE,0);I only get zeros.  I know that i am missing something but i can't figured out what... }  Anything you can point will be useful.  jairo

[Altera_Forum]

I recommend running a simulation of the design to make sure it's not actually returning 0 like the CPU is reading. You can simulate the design with your CPU code running to help recreate the issue you are seeing.

[Altera_Forum]

Hi, 

 what happens if you are using the memory window on the baseadress of your component? Are there only zeros, too? What setting have you done for your component in sopc? I mean the interface and timing in the sopc-builder (setup, read wait, write wait, etc.)? If you think write is ok and read makes trouble I would try to raise read wait.

[Altera_Forum]

Here you can see the input ouput Configuration 

 i53.tinypic.com/dlq235.jpg (http://i53.tinypic.com/dlq235.jpg)  An Here the settings for the avalon interface.  i56.tinypic.com/2vshlpv.jpg (i56.tinypic.com/2vshlpv.jpg)  We have changed the configuration to a IRQ Drived one. But despite we register the ISR the Software doesn't detect anything...  I' have no idea about what is the problem... Any help will be good.

[Altera_Forum]

Could you show us the HDL code for your component?

[Altera_Forum]

Hi, 

 you only have connected read and readdata. So the only thing you can do from Nios-side is read the data. Which values you want to read? If you have choosen "No, leave it blank" in "Mem Init" due the RAM initialisation there will only be zeros in it. How do you get something in the RAM?

[Altera_Forum]

Hi. 

I'm the Jairo's partner. I'm sending you our HDL. It's based on AN 473: Using DCFIFO for Data Transfer between Asynchronous Clock Domains.  Regards!!!

[Altera_Forum]

I don't use Verilog but from what I'm understanding in the read control logic it seems that you read the contents of the FIFO as soon as there is something in it, even if there isn't a read request coming on your component. Is that really what you want? 

It could be a good idea to use SignalTap to look at your signals and understand what is happening.

[Altera_Forum]

Hi, 

 I´m not sure but for me it looks like you don´t come back to IDLE. You only go from INCADR->WRITE->WAIT->INCADR. Is that your intention?

[Altera_Forum]

Hi. 

We've created a new simpler design. It consist in a state machine that puts a constant value at output, handled by some control signals.  This is the HDL:  pastebin.com/yMBeTWPz  We have been simulating it, and it seems to works in the way we want. Now, we just need to test it with SOPC and NIOS II IDE. It's been a long week for us. We'll do it on Tuesday.  Any suggestion will be welcome.  Regards.

[Altera_Forum]

This is a basic observation, so maybe I am missing something. I haven't read any of your verilog code, but you wrote that your C code was: 

 IORD(DCFIFO_DE_TOP_0_BASE,0);   You are not assigning it to any variable, like:   unsigned int result; result = IORD(DCFIFO_DE_TOP_0_BASE,0);   How do you know that the IORD is returning nothing but zero? Are you stepping through the assembly code?   After further examination of the verilog code in read_control_logic, like someone else pointed out:   "I´m not sure but for me it looks like you don´t come back to IDLE. You only go from INCADR->WRITE->WAIT->INCADR. Is that your intention?"   I concur. Not to mention that having a state named "WRITE" in a module called read_control_logic doesn't seem like a good practice, as you aren't writing anyting, and doesn't describe what you are attempting to do.   On the statement: "always @ (posedge clk_i or posedge reset_i or negedge read_i) begin"   the "or negedge read_i" part bothers me. I've never used that as a condition in an always.   "assign data_o = data_i" bothers me.   You do nothing with data_i in your code, so why pass it in and out? In dcfifo_de_top3.v, I would rename "q" as readdata, and put "assign readdata = fifo_out;" somewhere, and take out the unused ports of "data_i" and "data_o" in read_control_logic.v   Overall, I would suggest you try experimenting with the simplest avalon MM slave you can think of first (like returning a constant), verify you read the result, then progress in baby steps. You seem like you are trying to do too much at once for your level of understanding.

[Altera_Forum]

Luirro had posted a new verilog code that implements the smaller avalon mm slave device that we can make. 

 This is the HDL:  pastebin.com/yMBeTWPz   We conect it to the sopc, assigning the following pins:  Clk ==> clk_sink irq_port ==> interrupt sender ==> irq data_o ==> Avalon_Slave ==> readdata read_i ==> Avalon_Slave ==> read  We have declare the ISR, but nothing happens, if we force the reading, only zeros again... The componet works perfect.  Any ideas?  Jairo

[Altera_Forum]

When Jairo says "the component works perfect", he means that we've simulated the HDL (in quartus and modelsim) and it works like we want it does. 

 Regards.

[Altera_Forum]

Ok, there is a simpler code: 

module simpler ( data_o, address_i, clk, read_i ); output reg data_o; input address_i; input clk; input read_i; always @ (posedge clk) begin data_o = 32'hF0F0F0F0; end endmodule  This only puts a constant on readdata whatever the inputs are.  And there is the Nios2 sofware side... it still reads Zeros...  #include "basic_io.h"# include "Test.h"# include "LCD.h"# include "DM9000A.C" int main(void) { unsigned int res, i; for(i=0; i < 255; i++) { res = IORD(SIMPLER_0_BASE, 0x00); printf("\nIteracion %d, res =%d", i, res); msleep(500); } return 0; }   sorry for being so annoying

[Altera_Forum]

That's really strange... Are you sure that your component is connected to the Nios data master port? In the component editor, are you sure that data_o is defined as readdata on the slave interface?

[Altera_Forum]

Hi again, 

 I just read your thread again. I´m not really sure wheres your problem but I wanted to help you. I created a really simple read & write component for SOPC builder. I attached the screen of the SOPC, the main.c programm I tested the component with and the Verilog file with the tcl file. If you use the component with my tcl you should not get any problems to read or write from it.

[Altera_Forum]

Hi Jacol... thanks a lot. 

 A question: Did you build your SOPC design from zero? O did you just adapt an existing design?  Regards

[Altera_Forum]

I don't know what's happening but we test you design and it doesn't work. Can you send me the entire project?? 

 my email es jairotrad (at) gmail (dot) com  Greetings!

[Altera_Forum]

Hi guys. 

 Finally, we could make our project worked. We did it!! Thanks everyone.... but, now we have another problem.  We want our device to work as an interrupting one. So, we wrote a code as follows:  pastebin.com/U3xfZXrY  And this is our modified HDL:  pastebin.com/Xypads8f  We simulated it, and it apparently works, but when we want to run at NIOS EDS, it doesn't work..  Any suggestions?  Thanks a lot!!!

[Altera_Forum]

About your C code: 

you shouldn't call printf() from an ISR. It will probably try also to use interrupts, and it can freeze the system. Instead, define a global variable, change its value inside the isr, put the printf() in your main() function and have it print something when the contents of the global variable changes.  About your Verilog code: put everything inside the always @ (posedge clk_i) block. You shouldn't use the signal read_i as a clock. Instead, detect changes in read_i by comparing it to its previous value inside the main block that depends on clk_i. Using a signal as a clock will lead to all kind of problems on your design, including transitions at unwanted moments due to glitches.

[Altera_Forum]

Hi daixiwen. 

 Our problem is: we need to detect the change of the signal read_i.  1) We send a irq request. 2) The Avalon Master detects our request, so, it asserts the read_i and we need to desassert irq_req. 3) When the device stops the reading, it dessaserts read_i, and then we have to go to INCADR state, to get the next data from a FIFO and putting it as output.  I can't understand how I could do it the way you said.  Thanks.