DDR2 Read-Write-Read-Write Example

[Altera_Forum]

Hello, I'm looking over the DDR and DDR2 SDRAM Controller Compiler User Guide and my question is on page 3-30. Here they show a Read-Write-Read-Write example and we see that is the order of the local_read_req and local_write_req signals, but it appears that the write occurs then read, then write, then read. I'm looking at the order of the local_wdata_req and local_rdata_valid signals. Can anyone explain what is happening here? 

 Thanks, joe

[Altera_Forum]

Hi Joe306, 

 The timing looks "twisted" because of the fact that when you are doing a write the controller needs the data right after the write command and for reads the data appears after the controller has read the data from the memory.  So, when you think about writes, then the controller would need to have the data to be written to memory just after it issues the actual "WRITE" command to memory. In order to have the data to be transferred to memory available for the transaction the controller will ask for the data from the user early enough (to be buffered internally etc.)  Reads work differently; the controller will first issue the "READ" command to the memory, after which it has to wait for a number of clock cycles for the controller to fetch the data from memory. Only after the data is read from the memory can the controller give the data to user, i.e. assert the local_rdata_valid. If you look carefully at the DDR SDRAM interface waveforms (especially ddr_dq and ddr_dqs) and the local_rdata_valid signal you can see that local_rdata_valid signal gets asserted right after the data is read from the memory.  I hope that makes sense..

[Altera_Forum]

The memory actions are in the same order as requested at the local interface. But local_wdata_req occurs before physical write and local_rdata_valid after physical read. As a consequence, you have to process read and write pipeline independantly at the local interface.

[Altera_Forum]

Hello, thanks for responding to my post. I have another question and it relates to the signal "local_size". I am using a PCIe card that has some DDR2 SDRAM installed. I hope to do a DMA to the card into an FIFO on the fpga and then read the fifo and write the data to the SDRAM. The amount of data could be large, say a 512by512 32 bit image. In that case would I have any problem setting the local_size signal to be 1?  

 On page 3-25 it has a note for DDR2 device with the local_size signal. It says,  "The concept if similiar for DDR2 SDRAM althought only burst lengths 1 and 2 (2 and 4 on the DDR2 SDRAM side) are available."   I'm confused, does that mean the size choices are only 1 and 2 for the signal local_size?

[Altera_Forum]

--- Quote Start ---  does that mean the size choices are only 1 and 2 for the signal local_size?  --- Quote End ---  Yes, but the DDR2 controller is achieving continuous data flow within the same RAM page anyway (except for the necessary refresh cycles).

[Altera_Forum]

Hai, 

i am trying to store datas in ddr_sdram mem.I have university program license.Using that license i can access ddr_sdram controller in the megawizard.Is it enough to access sdram or Need to purchase IP.please expain   I didnot have hardware,can i verify my codings of sdram through using niosii simulator.is it possible? please explain PLEASE HELP ME