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PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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PCIe Avalon-MM 32-bit reads

Altera_Forum
Honored Contributor II
‎07-20-2010 08:17 PM
978 Views

Is the PCIe Avalon-MM implementation limited to 64 bit transfers? I'm not seeing the PCIe IP use the Avalon byteenables correctly to size the transfer. Is the IP limited to only supporting 64-bit accesses?

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Altera_Forum
Honored Contributor II
‎09-23-2010 12:15 AM
238 Views

Did you ever figure this out, I am wondering this myself. I am having a problem because it accesses a register that triggers an event on a read.

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