Re: Multiple Clock

Altera_Forum · ‎02-28-2005

Hi everyone,

I try to implement a system with multiple clock domains. The NIOS system run with 50 Mhz and some avalon components should run with 100 Mhz (DMA, FIFO, internal SRAM). SOPC Builder build this system without a problem. But during the "Analysis & Synthesis" I got several errors. So I have tried to build the system that is descriped in "Building Systems with Multiple Clock Domains" but the same errors occured.

Has somebody made the same expericences ? Or build a working system with multiple clock domains.

regards

revolt

Altera_Forum · ‎03-01-2005

Hi!

I think you can try to get the other clocks from a fast clock by using PLL.

Altera_Forum · ‎03-01-2005

The clock generation is not the problem.

The clock-domain crossing logic that is created by the SOPC builder can not be synthesised or simulated.

Altera_Forum · ‎03-01-2005

Add SignalTap II to the list as well.

I used a seperate clock for a custom peripheral on a uKit board, it built and works fine. The periperhal clock was 1/3 slower than system. Both clocks originated from same PLL.

Have you tried a faster clock for CPU and slower for other, just as a test?

Altera_Forum · ‎03-02-2005

I found the problem during the sythesis. SOPC Builder creates for the clock domain crossing logic:

endofpacket_bus_pipe : dma_0_control_port_slave_X_cpu_data_master_bus_pipe

port map(

data_out (31 DOWNTO 1) => open,

data_out (0 downto 0) => internal_slave_endofpacket,

clk1 => slave_clk,

clk2 => master_clk,

data_in => std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(master_endofpacket)),

reset_clk1_n => slave_reset_n,

reset_clk2_n => master_reset_n

);

Quartus doen't like this line : data_out (0 downto 0) => internal_slave_endofpacket,

after changing to data_out (0) => internal_slave_endofpacket,

synthesis works without a problem, but modelsim show some other problems http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif

@joelw: no I didn't try. But I will do.

Altera_Forum · ‎03-02-2005

@joelw: Now my NIOS is fast then my fifo, but the errors are still the same.

Altera_Forum · ‎03-07-2005

Hi there,

I had the same problem. Make sure you are running the service pack for 4.2. This fixes things.

Good Luck.

Altera_Forum · ‎03-09-2005

hi sja,

thx for the hint. Now synthesis runs without a problem. Did you try to simulate your design with Modelsim?

There I get still errors.

Altera_Forum · ‎03-09-2005

Hi there revolt,

Sorry. I didn't go down the Modelsim path so I can't offer any suggestions there.

I hope you work it out.

Good luck

sja