Re: assignments.

Altera_Forum · ‎10-31-2007

How can I assign a std_logic_vector type output a value of 9?

Quartus says integer literal not matched or something.

if q: OUT std_logic_vector(3 downto 0);

can i do:

q<= '1001';

I tried to create a variable and give the variable of integer type a value of 9 then do:

q <= variable;

I need to know how to assign data to std_logic types.

The only reason I want to do this is because:

I need the code :

q <= (others => '0');

And this only works when q is a std_logic type.

The reason i need this is because there is a bug in the altera chips in my college, where if i press reset using pushbutton, it will show 00 when i hold it down, then when i release, it will go back to whatever was previously on the seven segment display. I want it to reset to 00.

Altera_Forum · ‎10-31-2007

If q is a std_(u)logic_vector, you can write

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q <= "1001";

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which type is your variable ? maybe you have to "transtype", for exemple

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q <= std_logic_vector(variable);

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if variable is unsigned(3 downto 0).

Your 'reset' seems to be active low (when its value is '0', the reset is active), because of voltage controller and/or (in your case) push button usually sets to 0.

In an other way, you probably have a reset_n button.

++

Altera_Forum · ‎10-31-2007

You could do a couple of things, either:

a) Make q an intager, not a STD_LOGIC type, ie.

SIGNAL q : INTEGER;

and then

q <= 0;

...to reset it. Or:

b) Use a conversion function:

q <= CONV_STD_LOGIC_VECTOR (variable, 4);

...'4 being the width of vector you want to convert to.

Altera_Forum · ‎11-01-2007

thanks for the reply guys. I am running into one problem now that is stopping my program from working.

In std_ulogic_vector ...quartus 2 does not understand the operator +. here is a sample of my code:


IF (q_one="1001" and q_ten="1001") THEN
       q_one <= "0000";
       q_ten <= "0000";
ELSE
	q_one <= q_one + "0001";
END IF;
						
IF (q_one=10) THEN
	q_ten <= q_ten + "0001";
	q_one <="0000";
END IF;

i want to increment q_ten and q_one by 1. this was working when they were integer types but then I couldnt use, the q_ten <= (others => '0'); code it is too much work for me to change the type ...unless i do conv function, but how can i correct this in the easiest way?

Altera_Forum · ‎11-01-2007

hey actually i fixed it. I changed my inputs and outputs to type 'unsigned'. and everything is fine now.

but i still dont truly understand the differences between types.

how is std_logic superior to unsigned when it cant be assigned integers where unsigned can take both integer and binary?

Altera_Forum · ‎11-07-2007

Use

library IEEE;

use IEEE.std_logic_1164.all;

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Les bibliothèques std_logic_arith, std_logic_signed et std_logic_unsigned, malgré leur nom, ne sont pas normalisées par l'IEEE et leur utilisation est fortement déconseillée. En effet, il est préférable de préciser explicitement le type de chaque vecteur sur lequel on fait une opération (SIGNED ou UNSIGNED) de manière à specifier son traitement arithmétique. Le comportement des opérations sur les types STD_LOGIC_VECTOR sera différent selon la bibliothèque appelée, ce qui rend leur utilisation hasardeuse.

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(Sorry it's french)

To resume, use unsigned or signed for arithmetic operations

Use

library IEEE;

use IEEE.std_logic_1164.all;

integer signals must be bounded if employed.

use integer for generic parameters.

Use sdt_logic, std_logic_vector for entity ports. compatibility reason.

Altera_Forum · ‎11-12-2007

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In std_ulogic_vector ...quartus 2 does not understand the operator +. here is a sample of my code:

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Add these lines in your code:

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

It may help、

Good luck.

Altera_Forum · ‎11-04-2008

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Add these lines in your code:

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

It may help、

Good luck.

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With this lines, You have in mind that quartus will interpret std_(u)logic_vector as unsigned

Altera_Forum · ‎11-04-2008

I would use IEEE.numeric_std.all;

This is a proper standard IEEE library. The std_logic_signed / unsigned and std_logic_arith are not standard packages - Mentor and Synopsis have different implementations. The packages are just naughtily compiled into the IEEE library.