Trying to understand hold time violation

[Altera_Forum]

Hi, 

 I got this hold time violations in my design but couldn't find out what's wrong. I would appreciate if anyone could shed some light on this.  In the attached screenshot, I have highlighted the first path that gives a -11.361ns hold time slack, which was probably caculated by using Data arrived time minus Data required time (7.769 - 19.130).   What I don't understand is: why does the data required time have to include the clock period (15.625ns) in it?  If an launching clock edge happens at time 0 ns. it will reach the sending register at 3.329 ns. So the data is launched from the sending register at time 3.329, it will reach the input of the latching register at the time 7.769 ns. Then it will wait there for the latching clock edge. At 15.526 ns, the second launching clock edge and the first latching edge happened at the clock source and at 15.526+3.329 ns, they arrived at both the sending and receiving register. If there are propagation delays it will have positive or negative impact on the hold time requirement.  Now the data at the input of the receiving register needs to be stable for a certain period of the time, which is the required hold time for the receiving register (0 ns). The only thing can cause the data to change is the new data driven from the launching register, which has been launched and will arrive in 7.769-3.329=4.44 ns. This will give this circuit a 4.44 ns POSITIVE hold time slack.  But the Timequest reported an -11.361ns slack.  Am I missing something here? Your comment will be very much appreciated.  Thank you. Hua

[Altera_Forum]

There's something strange going on, but I can't tell from the diagram. You're right that the default hold requirement should be 0ns(launch at 0ns, latch at 0ns). My first guess is that you have a setup multicycle of 2 on this path. The default hold requirement is based on the setup requirement, so adding setup multicycles moves the default hold requirement. The way to fix this is to add a -hold multicycle of 1.

[Altera_Forum]

You were right on, Sir. Thanks much. 

 Hua