Mega Wizard FIR compiler HELP

[Altera_Forum]

I have some questions about the FIR compiler in Quartus 7.2. Would be very thankful if you could help me. 

I am using a Cyclone 2 on a DE2 board. And no English is not my native language.  It only says it wants a clock, not what frequency. What frequency does it want, sampling frequency, in my case 48000(sampling freq) or the 50MHz clock?  If I am already in a project when i create a FIR filter, are all files automatically included or do i have to include files manually? It generates a lot of files.   I am using block schematic, what file do I have to use in the schematic. just the "filter.vhd" file?  My "filter.vhd" block has several inputs and outputs Left side (inputs) CLK, reset_n, ast_sink_data[7..0], ast_sink_valid, ast_source_ready and ast_sink_error[1..0]  I now send ~48000 (little higher) on CLK  Reset is active low  ast_sink_data, constant flow of samples that are updated at freq of ~48000 and then keep that value until next value is done.  ast_sink_valid, no idea what this does, tried to just connect it to ast_source_valid of the same block, did not work. What do i send here? ast_source_ready, no idea here either. Is it constant 1 on both? ast_sink_error, no idea here either, read somewhere that you could just send 00 . Left side (outputs) ast_source_data[16..0], ast_source_valid, ast_sink_ready and ast_source_error[1..0]  I guess ast_source_data[16..0] is the filtered data. The rest is if you connect several blocks I figure. Which I will do later, but want to try do make one filter first.  Any other pointers would be great.

[Altera_Forum]

Update. 

CLK is connected to 50MHz clock On the ast_sink_valid I have a ~48000 CLK ast_sink_error is stuck to ground (00) ast_source_ready is stuck to 1  Data is updated with a freq of ~48000 (same freq as ast_sink_valid).  I am getting values that indicate that the filter is working, but I get very high values. I have a 123 order lowpass fiter with a cutoff freq of 10KHz. It should be very quiet when over 10Khz but the difference between them is very small. I am using the LED to produce a stack with 24 levels to look at the amplitude of the filter output. Any ideas of what I am doing wrong?

[Altera_Forum]

Hi Machinae, 

 According to figure 3.18 in FIR Compiler User Guide You are right with ast_sinh_valid, ast_source_ready and clk.  But I have some questions to You...  1. Your filter is single-rate or multirate? 2. How do You testing Your design? You're simulating it in quartus?  I think it will be good if You paste here some screenshots. I also have some problems with FIR Compiler and maybe we'll get over it together.  Best regards,  Marcin

[Altera_Forum]

I got it working using this configuration 

CLK = 48000hz CLK ast_sink_valid = logic 1  ast_sink_error is stuck to ground (00)  ast_source_ready = logic 1  But I have 7 lowpass filters and 24 bandpass filters and using parallel design takes to much LE:s. Below is my design in Simulink (easier to understand) http://static.pici.se/pictures/SACiIinKq.png  I am using downsample and lowpass filters to look at 24 frequencies from 0 to 20000 hz. By downsampling I can use the same filters. Simulation works fine. I tried using muxing to use the same filter and sending it another clock speed and data from another lowpass filter since I only need to update my values about 6-10 times per second. Did not work, seems it doesn't like changing clock speed. So now I am using low order parallel filters. But since I have some time over (actually I have all the time in the world but me and my classmate want to start writing report next week) I have tried switching to serial filters since they take up less LE:s.  So if you have gotten a serial filter to work please tell me how cause mine does not work. This is what I send my serial filters.  CLK = tried using 50 MHz (my teacher told me to), then I tried using 8 times sample speed (have 8 bit resolution on my sound, 8 highest bits) then i tried using 15 bit resolution (15 highest bits) and clockspeed of 16 times higher clk speed then sample speed. The manual states that the filter in general (not always wtf?!) wants new data every "number of bits +1" clockcycle. So in my case 16 times the samplerate.  ast_sink_valid = high one clockcycle in the same speed as samplespeed. as stated by manual see screenshot. In screenshot of simulation, CLK is 16 times samplerate, RST is high cause reset is active low. sink:reg is the counter from 0 to 15 to set S_VAL (sik_valid) high for one clockcycle. http://static.pici.se/pictures/QGIhWizqr.png   ast_sink_error = stuck to ground (00)   ast_source_ready = logical 1   one problem I figure could be it, next on my to do list, is that I always read the output and maybe I shouldn't do that. Still it should not cause these problems I have. Since well now just about nothing happens. If I press reset I see some diodes flashing quickly then nothing. This is my thesis work (well not just this but this is the hard part) and I dont really have to get these serial filters to works since I have a working design with parallel filters, but I want higher order filters. So anyone have a working serial filter I would be very VERY glad if you could help me.