Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20737 Discussions

MAX700AE pin info

Altera_Forum
Honored Contributor II
‎12-06-2010 03:09 PM
895 Views

Dear all, 

 

I'm watching the Chip Planner view of a MAX7000AE device (EPM7064AETI44-7). 

 

On the top left I see four pins (unused in my combinatorial circuits while one of them is used in sequential circuits) that are named FINPBUF[4:1]. 

 

Are these clock, reset, oe and global clock pins? 

 

What is acronym for? 

 

Thx.
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.