including various design files

[Altera_Forum]

Hi all, 

 I've created a couple of different design files for testing purposes and now want to combine all in one file, rather than writing them all out again.   So I've created a new project and included each design file. What I'm unsure about is how to actually include them when writing my new VHDL file. I've tried to find samples on here but can't seem to locate any.   For example, how do I take the output of one as the input of the next? If it would help to see the program I am working on I can post it.    Thanks for any help.

[Altera_Forum]

The required method is component instantiation. The Quartus PDF tutorial for VHDL users or the Quartus VHDL templates shows the syntax. Also any VHDL text book.

[Altera_Forum]

I find it really tedious to write vhdl just for conneting blocks. Personally I like connecting blocks using schematics.You can generate symbols for your vhdl block easily: file->Create symbol. But of course its a matter of taste what you prefer.

[Altera_Forum]

--- Quote Start ---  I find it really tedious to write vhdl just for conneting blocks.  --- Quote End ---  There are more options than simply connecting blocks, e.g. generated structures and design variants. But whatever you prefer for your top design level, you need the component instantiation syntax to write structural VHDL code.