Problem with flash programmer

[Altera_Forum]

Hi, 

 I am sure it is a beginner problem but I am not able to find an answer in the help of NiosII.   I would like to program my FPGA (http://www.altera.com/products/devkits/altera/kit-dsp-2s60.html) with a .sof file.    So I create a new project hello_world with a niosII_stratixII_2s60\full_featured SOPC builder.  then I go to the flas progammer, I choose my project. Project and SOPC builder are recognized.  Then I select the box "Program FPGA configuration data into harware-image region of flash memory". I disselect "Program software project into flash memory).  I choose my .sof file Then I choose my hardware Image, I have two choices: factory U5+0xC00000 or user: U5 + 0x800000. I choose the second ( but it dosnt work with the 2 configurations).  I switch on my board, Then I click on Program flash.  Building and conversion to flah file are OK.  then he tells me: "# Programming flash with the FPGA configuration $SOPC_KIT_NIOS2/bin/nios2-flash-programmer --device=1 --sidp=0x021108C8 --id=203 2497071 --timestamp=1145613411 --base=0x00000000 full_featured.flash There are no Nios II processors available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary. "  I had a look to the ug_nios2_flash_programmer:   Probable Cause The flash programmer is unable to connect with a Nios II JTAG debug module inside the FPGA. Suggested Actions ■ Make sure that the FPGA is running a valid flash programmer target design. If not, you need to configure the FPGA using the Quartus II programmer. See “Flash Programmer Target Design” on page 1–3.  What does that mean??? I had a look on page 1-3 and they say to use the full featured SOPC builder (as i did).  I have tried some others configurations but none allow me to go further than the config I have described.  Can someone help me ?

[Altera_Forum]

If I'm not mistaken, I think you have to have the firmware (with NIOS core) programmed into the FPGA at least once before you can program using this method. So, program your sof file using the Quartus programmer for the very first time and then repeat what you have done. Once the NIOS firmware is in FLASH and can be booted at power-on, you should be OK.

[Altera_Forum]

Ok, I have loaded my program with the Quartus programmer and then redone what I described before......... 

 But that does not work :(   Always the same mistake

[Altera_Forum]

Why did you uncheck 'Program software project into flash memory'? Is there no Nios II program you want to load? If so, you could use the Quartus Programmer instead of the Flash programmer.  

 For only loading a .sof file to the flash, you can go to File-> Convert Programming Files..-> choose e.g. .jic File as programming file type -> choose the right flash device -> click on Flash Loader and choose your FPGA type -> click on SOF Data and choose your .sof-file -> generate. Then in the Quartus Programmer you can choose that .jic File and start programming the Quartus. Every reset of your board the configuration will be loaded from the flash into your FPGA, because you added a Flash Loader.  BTW, I got that 'There are no Nios II processors available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary.' message for several reasons already. Once I had some wrong clk assignements in the SOPC Builder, or in the Assignement Editor, or one of my user components have not been programmed well yet. In all that cases I got that message, just because the FPGA configuration was 'bad'. And sometimes it helped just to shut down the Nios IDE and the Quartus, or sometimes it was enough to only close and reopen the Quartus Programmer or once it helped to restart the PC. But the real reason for that message was one of the errors descriped before, what turned out later. Same happened to a colleage. Just to be complete about that error message.

[Altera_Forum]

Thanks for your tips 

  Why did you uncheck 'Program software project into flash memory'? Is there no Nios II program you want to load? If so, you could use the Quartus Programmer instead of the Flash programmer.  I have only some VHDL code, I have written this code in Quartus, but in the Help they say to use Flash Programmer for a non-volatile configuration. So i jus use a hello_world project to have a project but I don´t cate about what this program does. I just want to load my .sof file.  For only loading a .sof file to the flash, you can go to File-> Convert Programming Files..-> choose e.g. .jic File as programming file type -> choose the right flash device -> click on Flash Loader and choose your FPGA type -> click on SOF Data and choose your .sof-file -> generate. Then in the Quartus Programmer you can choose that .jic File and start programming the Quartus. Every reset of your board the configuration will be loaded from the flash into your FPGA, because you added a Flash Loader.  But i want more than every reset, i want to have my configuration even if I power down the board.  I´ve tried but this error always occure: Error: Can't recognize silicon ID for device 1  I don´t know what that is. I am forced to use EPCS64 for flash device because for the others configuration he told me there is not enough memory ( my .sof file is 1.886 KB and the .jic file 8.193 KB :eek: ). Actually, the EPCS16 could be well but he doesn´t want....  BTW, I got that 'There are no Nios II processors available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary.' message for several reasons already. Once I had some wrong clk assignements in the SOPC Builder, or in the Assignement Editor, or one of my user components have not been programmed well yet. In all that cases I got that message, just because the FPGA configuration was 'bad'. And sometimes it helped just to shut down the Nios IDE and the Quartus, or sometimes it was enough to only close and reopen the Quartus Programmer or once it helped to restart the PC. But the real reason for that message was one of the errors descriped before, what turned out later. Same happened to a colleage. Just to be complete about that error message.  I think my pin assignments are right because when I load my .sof file it works.

[Altera_Forum]

i have only some vhdl code, i have written this code in quartus, but in the help they say to use flash programmer for a non-volatile configuration. so i jus use a hello_world project to have a project but i don´t cate about what this program does. i just want to load my .sof file. 

If you only have some VHDL code, there is no need to add a Nios cpu in SOPC Builder, you can delete it, if it's already there or at least, if you need it as avalon master, use the smallest Nios cpu ('e'). This will reduce your configuration size, too. Without Nios cpu, you don't need any Nios program either.   but i want more than every reset, i want to have my configuration even if i power down the board. Sorry, I wrote it imprecise, if you program the flash with a .jic-file, of course you will also have the configuration present after power down, it will be reloaded automatically from flash with the next power up.  i don´t know what that is. i am forced to use epcs64 for flash device because for the others configuration he told me there is not enough memory ( my .sof file is 1.886 kb and the .jic file 8.193 kb ). actually, the epcs16 could be well but he doesn´t want.... In 'Convert Programming Files...' you could go to 'Options' and click 'Compression Mode', but I've never tried, maybe first read some documentation about that.  error: can't recognize silicon id for device 1 I saw that error already, but sorry, I don't remember what was wrong that time. Maybe somebody else can answer this or you can find an answer in this forum. But first you could try the things described, maybe then this error is cleared.  i think my pin assignments are right because when i load my .sof file it works. I also think so, it was just a general comment to that error message.

[Altera_Forum]

Currently, I always am not able to make a non volatile configuration. Always the same mistake occures: 

 Error: Can't recognize silicon ID for device 1  Can someone help me??  Thanks

[Altera_Forum]

I have two comments.  

1. with Cyclone III, I sometimes experienced the PFL IP not working correct within the current design for unclear reasons, also reporting can't recognize silicon id for device 1. It turned out, that the AS pins didn't operate as they should in this situation. In one project, that initially could use SFL with Quartus 7.2, it didn't work any more after upgrading to SP3 to support CIIIC16. I suspect that there is a Quartus bug.   However, SFL could always be used with a blank design containing only SFL IP and having no pin assignments at all. Blank SFL configurations are also available vom Altera, I think, but can be easily generated. Although in some cases, it may be desirable to program and verify the flash using the target design, I finally accepted this restriction and usually bundle the jic file fith blank design sof and the cdf file for production purposes.  2. When the Programming File Conversion tool says, the design doesn't match the flash device, although the (compressed) sof is smaller than device capacity, you most likely forgot to set the compression switch in the conversion tool under (sof) input file properties. Having an compressed or uncompressed input file doesn't matter, this option has to be set in the tool a new.

[Altera_Forum]

2. When the Programming File Conversion tool says, the design doesn't match the flash device, although the (compressed) sof is smaller than device capacity, you most likely forgot to set the compression switch in the conversion tool under (sof) input file properties. Having an compressed or uncompressed input file doesn't matter, this option has to be set in the tool a new. 

 You are right, now it works  However, SFL could always be used with a blank design containing only SFL IP and having no pin assignments at all. Blank SFL configurations are also available vom Altera, I think, but can be easily generated. Although in some cases, it may be desirable to program and verify the flash using the target design, I finally accepted this restriction and usually bundle the jic file fith blank design sof and the cdf file for production purposes.  I am sorry, but I have not all understood. What´s SFL? I don´t understand what you purpose me to do:  I tried to send the .jic file with the Quartus II programmer, and I have this error:  Error: Can't configure device. Expected JTAG ID code 0x020930DD for device 1, but found JTAG ID code 0x120930DD.  I tried to send the .sof and the .jic but I have this error:  Error: Device chain in Chain Description File does not match physical device chain -- expected 2 device(s) but found 1 device(s).  But I am not sure it was what you mean

[Altera_Forum]

I expected, that you are accessing EPCS through JTAG cause you are converting to jic format. In this case a particular SFL (serial flash loader) Megafunction would been included to your design (hopefully). I reported a case where this megafunction wasn't operational although included correctly to the design. But I'm not sure about your design, but I can't imagine how the EPCS design could be programmed through JTAG without having a serial flash loader. 

 P.S.: If a similar serial flash loader function is also imported by SOPC builder but it doesn't work as expected, it may be meaningful to try loading the EPCS through a standalone serial flash loader as described in the serial flash loader documentations (AN370).

[Altera_Forum]

I am accessing my EPCS through JTAG. 

But I have not included any SFL Megafunction in my design... I dont know what it is and how it works...  Have I To do too something with the sopc builder??  Only 1 month I have this board, and it is the first time with altera products for me, so sorry if my answer is not very pertinent... Anyway, thanks for your replies

[Altera_Forum]

Two concurrent programming methods have been discussed in this thread:  

 1. Using Nios II Flash Programmer (which requires the EPCS serial flash controller module included to the NIOS II design and loaded previosly to the FPGA). Personally I'm not using NIOS II, so I can't give further hints regarding this method. See Nios II Flash Programmer User Guide for details.  2.Using standard Quartus Programmer and jic file(which requires the said SFL IP included to the design and loaded previously to the FPGA). My comments have been related to this method. See AN370 http://www.altera.com/literature/an/an370.pdf

[Altera_Forum]

I have followed step by step the AN370: 

-Conversion sof=>jic (with the compression, that is not mentionned in the an) -Generation of a SFL megafunction -Loading of the .jic   This error remains when I try to load my .jic: error: can't recognize silicon id for device 1   But I have a question about the SFL megafunction: When has the configuration been loaded to the FPGA in these step?? I have generated a VHDL file ( and a .cmp) but I never used it...   Or maybe it´s a malfunction case as you said in a previous post, but in this case I don´t know what else I can do...

[Altera_Forum]

My blank SFL design looks like this 

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY sfl_3c16 IS END sfl_3c16; ARCHITECTURE RTL OF sfl_3c16 IS COMPONENT sfl PORT ( noe_in : IN STD_LOGIC ); END COMPONENT; BEGIN sfl_inst : sfl PORT MAP ( noe_in => '0' ); END RTL;

[Altera_Forum]

LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY sfl IS PORT ( noe_in : IN STD_LOGIC ); END sfl; ARCHITECTURE SYN OF sfl IS COMPONENT altserial_flash_loader GENERIC ( enable_shared_access : STRING; lpm_type : STRING ); PORT ( noe : IN STD_LOGIC ); END COMPONENT; BEGIN altserial_flash_loader_component : altserial_flash_loader GENERIC MAP ( enable_shared_access => "OFF", lpm_type => "altserial_flash_loader" ) PORT MAP ( noe => noe_in ); END SYN; 

 Not exactly the same... I am going to cut/paste your blank sfl, i will see

[Altera_Forum]

Just a quick reset here: 

 The original post stated you had a EP2S60 DSP kit and then you were using the Stratix II Nios II project as a starting point. The Stratix II Nios II development board is not the same as the Stratix II DSP kit even though they both use the EP2S60 device. One of the differences between the two boards is that the DSP kit doesn't even have an EPCS device on it. The DSP kit uses a bulk flash device and a CPLD to configure itself.  I think you're going to have to create a simple Nios design with a parallel Flash Programmer and then create the JIC file to talk to that.

[Altera_Forum]

Yes, the DSP Dev Kit is using a parallel flash rather than an EPCS, I wasn't aware of that fact. The standard PFL programming file would use a *.pof type instead of *.jic for serial flash loader, but I don't know what's the NIOS II flow.

[Altera_Forum]

--- Quote Start ---   I think you're going to have to create a simple Nios design with a parallel Flash Programmer and then create the JIC file to talk to that.  --- Quote End ---    I have made a hello world project with a full_featured EP2S60F_ES device, launched ths Flah programmer, check the box "program FPGA configuration data into hardware image region of memory", uncheck all the others, choose my .sof file, chosen my hardware image (user:U5+0x800000).  and I have this error:  # Programming flash with the FPGA configuration $SOPC_KIT_NIOS2/bin/nios2-flash-programmer --sidp=0x021108C8 --id=2032497071 --t imestamp=1145613411 --base=0x00000000 training.flash There are no Nios II processors available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary.  ( EDIT: I have found a paralell flash loader in Plug in wizards, but it tolds me its not available with Stratix II, I can only chosse Serial flash loader)

[Altera_Forum]

This is the answer of Altera support: 

   --- Quote Start ---  You need to design a project with Nios II processor and the flash memory. And then, compile this project in Quartus II and configure the FPGA by the generated sof file. After that, in Nios II IDE, you can program the sof in the flash memory by Nios II flash programmer.  --- Quote End ---  

[Altera_Forum]

Sometimes it is useful to check 'Halt onchip configuration controller' in Options --> Programmer if your serial flash is empty