Synthesis hangs during "performing gate-level register retiming"

[Altera_Forum]

I'm an experienced Quartus user and I'm in the last leg of development for a new product, and all of a sudden I've started getting a hang every time I try and compile my project. It happens during synthesis, right after Quartus outputs this line: 

 Info: Performing gate-level register retiming  After that it doesn't output anything more, but continues to use the CPU, as if it's doing work. Its memory usage also gradually increases. I tried letting it run overnight to see if it would eventually finish, but it didn't. Eventually the computer runs of memory (it has 2 GB of RAM) and Quartus prints an out of memory error.  I think this hang is being exposed by something specific to my project, because I tried compiling another project on this computer and it worked fine.  I'm using Quartus II 9.0 SP2. The problem started on SP1 though.  Has anyone else seen this?

[Altera_Forum]

Something's causing that algorithm to go haywire. I'm sure it's design specific, so you might want to try filing an SR. Naturally turning of register retiming should help. You can also turn it off/on for specific hierarchies, just right-click on the hierarchy in the Project Navigator and Locate to Assignment Editor. The Assignment is Perform Register Retiming... 

You could globally turn it off, and then turn it on for a module that you know needs it. You could also leave it on and then do trial and error turning it off to try and figure out which hierarchy is causing the problem. (You could also compile sub-hierarchies as the top-level and see where it goes crazy...)

[Altera_Forum]

Thanks, I've made an SR like you suggested. 

 I actually already tried to disable this optimization step, but it seems to ignore my settings. I turned off everything in Settings -> Compilation Process Settings -> Physical Synthesis Optimizations but I still got the "Performing gate-level register retiming" message and the hang. Following your suggestion, I also tried setting "Perform Register Retiming for Performance" to Off for the top-level hierarchy in the Assignment Editor, but that didn't change anything either. :(

[Altera_Forum]

--- Quote Start ---  Thanks, I've made an SR like you suggested.  I actually already tried to disable this optimization step, but it seems to ignore my settings. I turned off everything in Settings -> Compilation Process Settings -> Physical Synthesis Optimizations but I still got the "Performing gate-level register retiming" message and the hang. Following your suggestion, I also tried setting "Perform Register Retiming for Performance" to Off for the top-level hierarchy in the Assignment Editor, but that didn't change anything either. :(  --- Quote End ---    Hi,  sometimes the Quartus database in the folder "db" is corrupted and deleting the database helps.   Kind regards  GPK

[Altera_Forum]

I had this some months ago. One area of the design was being debugged by another designer and the fixes were causing the register usage to increase. At some point, it caused these hangs while another small increase got Quartus to report that the design wouldn't fit. Increasing the size of the partition for that part of the chip then solved the problem. However, that may be a bit misleading, the partition was not reserved and other nets were routed through it to get access to IO pads so it may be a conflict of that type, and the timing of those nets was tight so it might be related to trying to meet difficult constraints. I was never able to pin it down exactly but partitioning might be another area to look at. 

 Note that if you are using incremental and something fails, it can sometimes be retained for future builds. I have had problems that were cleared by switching off incremental to force it to start again, that might be related to erasing the database files.   HTH George

[Altera_Forum]

For posterity's sake, here's the outcome of my SR. Altera was able to eventually track down the problem. It turns out that the problem was actually in my SDC constraints for TimeQuest, which makes sense because I experienced a hang in TimeQuest too after I last changed the SDC file and prior to the first compile where synthesis hung. 

 According to Altera's engineers, TimeQuest has some sort of "constraint resolution algorithm" that sorts and groups SDC commands or something, and my project had a lot of exotic constraints involving lists of clocks and the sum of them was tripping up this algorithm. But there is a simple workaround: if you group constraints together yourself then it can avoid the bug. So, for example, I had a lot of constraints like this:  for { set i 0 } { $i < $N } { incr i } { set_false_path -setup -from -to set_false_path -setup -from -to set_multicycle_path -hold -from -to 2 ... etc. }  The Altera engineers showed me that stuff like this can be replaced with the following much shorter constraints:  set_false_path -setup -from -to set_multicycle_path -hold -from -to 2  Doing grouping and collapsing like that throughout my project fixed the problem. They also said that they will fix the root issue in Quartus II 10.0.