Re: Simulator: Can't find corresponding node name...

Altera_Forum · ‎06-11-2007

Hello,

I have problems in the simulator of Quartus.

I designed a VHDL-Code with SIGNALs and so on and made symbol file of this, for a schematic. In simulation I get the warning for different SIGNALs:

Warning: Ignored node in vector source file. Can't find corresponding node name "HiP3:inst|io_in_syn" in design.

The specific signals aren't shown in simulation becouse they were not found.

There are other SIGNALs in the Code that are found and simulated correctly.

I inserted the signalname in the *.wvf with the Node Finder, therefore the signal should be in the design, and I'm very sure that the "io_in_syn[6]" IS in the VHDL-Code.

Does someone know, why this warning occurs and how I can simulate this signals?

I would be very thankful :-)

bye

Altera_Forum · ‎06-11-2007

--- Quote Start ---

I inserted the signalname in the *.wvf with the Node Finder, therefore the signal should be in the design, and I'm very sure that the "io_in_syn[6]" IS in the VHDL-Code.

--- Quote End ---

I wonder whether you used the appropriate filter in the Node Finder. "Design Entry (all names)" works for most things I do, but sometimes I have to use another filter. Is the node name you're having trouble with listed by the "Post-synthesis" filter for functional simulation or by the "Post-Compilation" filter for post-fit simulation? I have seen even register names be different post-synthesis versus post-fit.

Altera_Forum · ‎06-11-2007

hi,

thank you for reply.

The node which can't be found by the simulator only appears if I use "Design Entry (all names)". The other nodes also appear if I use a different filter than "Design Entry (all names)".

bye

Altera_Forum · ‎06-11-2007

If your node is a register, make the following assignments:

1. Preserve register

2. Add to simulation waveform

For the second assignment to work you must have "Automatically add pins to simulation waveforms" turned on in the settings dialog for the Simulator.

Altera_Forum · ‎06-12-2007

--- Quote Start ---

Hello,

I have problems in the simulator of Quartus.

I designed a VHDL-Code with SIGNALs and so on and made symbol file of this, for a schematic. In simulation I get the warning for different SIGNALs:

Warning: Ignored node in vector source file. Can't find corresponding node name "HiP3:inst|io_in_syn" in design.

The specific signals aren't shown in simulation becouse they were not found.

There are other SIGNALs in the Code that are found and simulated correctly.

I inserted the signalname in the *.wvf with the Node Finder, therefore the signal should be in the design, and I'm very sure that the "io_in_syn[6]" IS in the VHDL-Code.

Does someone know, why this warning occurs and how I can simulate this signals?

I would be very thankful :-)

bye

--- Quote End ---

You should use ModelSim-Altera to perform your simulations. Then you will have no problems with signals being synthesized away. Compile time will also vastly decrease.

Altera_Forum · ‎06-12-2007

--- Quote Start ---

If your node is a register, make the following assignments:

1. Preserve register

2. Add to simulation waveform

For the second assignment to work you must have "Automatically add pins to simulation waveforms" turned on in the settings dialog for the Simulator.

--- Quote End ---

I searched in Quartus Help for a while for "preserve" and changed the settings in the Assignmend Editor like this:

http://img527.imageshack.us/img527/6268/simuregisterspk0.gif (http://img527.imageshack.us/img527/6268/simuregisterspk0.gif)

But it doesn't help. The warnings stay the same and the nodes can't be find in a different filter than "Design Entry".

The "Automatically add pins to simulation waveforms" allready was turned on, so I don't had to change this.

bye

Altera_Forum · ‎06-12-2007

The "preserve" synthesis attribute in the VHDL file might work better than the "Preserve Registers" setting in the Assignment Editor. In the QII 7.1 handbook, see Volume 1, Section III, Chapter 8, pages 8-44 to 8-45.

Altera_Forum · ‎06-12-2007

--- Quote Start ---

I searched in Quartus Help for a while for "preserve" and changed the settings in the Assignmend Editor like this:

http://img527.imageshack.us/img527/6268/simuregisterspk0.gif (http://img527.imageshack.us/img527/6268/simuregisterspk0.gif)

But it doesn't help. The warnings stay the same and the nodes can't be find in a different filter than "Design Entry".

The "Automatically add pins to simulation waveforms" allready was turned on, so I don't had to change this.

bye

--- Quote End ---

Did you also make the assignment "Add to Simulation Output Waveforms"?

Altera_Forum · ‎06-12-2007

First I set the attribute:

SIGNAL memory_data:  STD_LOGIC_VECTOR(7 DOWNTO 0);
...
attribute preserve:	boolean;
attribute preserve of memory_data: signal is true;

than I set the option in the Assignment Editor:

http://img255.imageshack.us/img255/2327/simupreservedd1.gif (http://img255.imageshack.us/img255/2327/simupreservedd1.gif)

but it also doesn't work.

The signal I first tried to prevent from syntheziesing away was "io...." (see post befor). Now I changed my VHDL code and now the signal ist of the Type "Registered" and can be used for simulation without beeing synthezied away.

What could be another reason, that a signal is syntheziesed away?

Altera_Forum · ‎04-23-2009

时序仿真的时候

添加信号要从node finder的对话框里面选取，直接指定节点名可能会找不到指定的节点。

Warning: Ignored node in vector source file. Can't find corresponding node name "clk" in design. clk根本就没有这个信号啊？

例： 激励名叫 CLK －》从node finder里指定节点为－》clk1 －》 编辑激励波形 －》仿真

我没有仔细研究过，有一下几点仅供参考：

确定找的到的： 输入 pin ， 寄存器输出

确认找不到的： 综合时被优化掉的信号，比如： a<=b ;那你可能只能找到b，确找不到a；

或者

process（clk）

if clk'event and clk='1' then

b<=a;

c<=a;

end if;

end process;

那可能只能找到b，找不到c。:eek: :eek:

Altera_Forum · ‎03-08-2010

hi,

I have implemented the design in verilog and I am also facing similar warning issue. pecifically, the warnings read like this:

"Warning: Ignored node in vector source file. Can't find corresponding node name "pll:pll_inst1|c0" in design."

Would you please tell me the solution of this problem.

Thanks

Kapil