who can help me?my jtag can't connect my board

[Altera_Forum]

dear all: 

 i use Altera Debug Client Monitor Program ,in front of my config are correct,after i compile the light.s file ,but it can't load    Compiling source files... nios2-elf-as --gstabs -I D:/altera/72/nios2eds/components/altera_nios2/sdk/inc F:/project/FPGA/light/app_software/light.s -o F:/project/FPGA/light/app_software/light.s.o  F:/project/FPGA/light/app_software/light.s:0: Warning: end of file not at end of a line; newline inserted Linking... nios2-elf-ld --defsym nasys_program_mem=0x800000 --defsym nasys_data_mem=0x800000 --section-start .exceptions=0x800020 --section-start .reset=0x800000 -e _start -u _start --script D:/altera/72/nios2eds/bin/monitor/build/nios_as_build.ld -g -o F:/project/FPGA/light/app_software/light.elf F:/project/FPGA/light/app_software/light.s.o  ELF generated at F:\project\FPGA\light\app_software\light.elf. nios2-elf-objcopy -O srec F:/project/FPGA/light/app_software/light.elf F:/project/FPGA/light/app_software/light.srec  SREC generated at F:\project\FPGA\light\app_software\light.srec.     the selected jtag cable is either not connected to a board, or the board is not switched on.   waitting for it!

[Altera_Forum]

I am sure you would have powered on the board. So that possibility is ruled out. What remains is the JTAG connection. Three possible causes of error are there: 

 1. You haven't downloaded the correct .sof file to the FPGA. 2. If you are configuring from a configuration device or flash, then the configuration device/flash don't have the correct image (.pof). 3. The cable that you use is not correctly configured.