Syntax Error

[Altera_Forum]

can anyone tell me whats wrong with this code? :confused:  

 My device is  Family : Cyclone Package : FBGA Pin Out : 256 Speed Grade : 6 Name : EP1C12F256C6  My code: ----------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity allT is port(g, y, r : buffer std_logic(1 to 4); clk : in std_logic); end allT; architecture behav of allT is signal d, q : std_logic; signal gL : std_logic_vector(1 to 16); signal yL : std_logic_vector(1 to 4); component delay port(D, clk : in std_logic; Q : out std_logic); end component; begin process(r, clk, x) begin if (clk'event AND clk = '1') then d <= '1'; case r is when "0111" => g <= "0001"; when others => null; end case; for gL in 1 to 15 loop greenL : delay port map (d, clk, q); gL <= gL + 1; end loop; case r is when "0111" => g <= "0000"; when others => null; end case; case r is when "0111" => y <= "1000"; when others => null; end case; for yL in 1 to 3 loop yellowL : delay port map (d, clk, q); yL <= yL + 1; end loop; case r is when "0111" => y <= "0000"; when others => null; end case; case r is when "0111" => r <= "1011"; when others => null; end case; end if; end process; end behav; -------------------------------------------------------  When i compile this code, i get 4 errors.  Error (10500): VHDL syntax error at allT.vhd(35) near text "port"; expecting "(", or "'", or "." Error (10500): VHDL syntax error at allT.vhd(35) near text ";"; expecting ":=", or "<=" Error (10500): VHDL syntax error at allT.vhd(54) near text "port"; expecting "(", or "'", or "." Error (10500): VHDL syntax error at allT.vhd(54) near text ";"; expecting ":=", or "<=" --------------------------------------------------------  i'm new member here, please tell me if i make an illegal act or something wrong in this forum..thanks..:D

[Altera_Forum]

Hello, 

 it's not illegal to ask with coding problems.  The first thing I suggest is to let Quartus show the error line, that's simpler than counting source code lines.  for gL in 1 to 15 loop greenL : delay port map (d, clk, q); gL <= gL + 1; end loop;  Your instantiating a component in sequential code (in a process). Components can only be instantiated in concurrent code. Furthermore the usage of the component makes no sense at all, cause identical d and q signals are used in multiple instances. It's also not possible to increment a loop variable. I don't see clearly, what your trying to achieve here.  Regards, Frank

[Altera_Forum]

for gL in 1 to 15 loop greenL : delay port map (d, clk, q); gL <= gL + 1; end loop; 

 for yL in 1 to 3 loop yellowL : delay port map (d, clk, q); yL <= yL + 1; end loop;  what i'm try to do here is..i want to delay the earlier signal..thats mean for 15 and 3 clock cycle..is that i write the right code? :rolleyes:

[Altera_Forum]

What you wrote is not correct to "delay the earlier signal". It sounds like you want to have a series of D-FlipFlops to delay the signals either 15 or 3 clocks. But looking at the code posted, this may be the least of your problems. d is set to '1' so you'll see X's at startup until there is a rising edge of clk. Then there is no need for a delay because q will always be '1'. 

 The sensitivity list has x in it, yet x is not declared. And there are mulitple case statements for r that sets g and y to different values when r is "0111". And r is in the sensitivity list. It does not need to be.   There is also no reset condition.

[Altera_Forum]

thank for your respond gmpstr..this is 1st time using Quartus II..actually what I want to do is to make a traffic light controller..let me explain my code..(for my opinion it should do as follows)..there are 4 trafffic lights..and it should be work in sequential order..1 to 4 and back to 1.. 

 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; (g, y, r is for green, yellow, and red..there will be four each of them.. 1 to 4..1 is the 1st traffic light and 4 is the last traffic light..) entity allT is port(g, y, r : buffer std_logic(1 to 4); clk : in std_logic); end allT; architecture behav of allT is (this signal I made here is for the delay part) signal d, q : std_logic; signal gL : std_logic_vector(1 to 16); signal yL : std_logic_vector(1 to 4); component delay port(D, clk : in std_logic; Q : out std_logic); end component; begin process(r, clk, x) begin if (clk'event AND clk = '1') then d <= '1'; (here i use the CASE statement to look at red light to on the green light) case r is when "0111" => g <= "1000"; when "1011" => g <= "0100"; when "1101" => g <= "0010"; when "1110" => g <= "0001"; when others => null; end case; (this part is to make the green light on for 15 clock cycle) for gL in 1 to 15 loop greenL : delay port map (d, clk, q); gL <= gL + 1; end loop; (after 15 clock cycle..the green light will be off) case r is when "0111" => g <= "0000"; when others => null; end case; (and its time for the yellow light to on) case r is when "0111" => y <= "1000"; when "1011" => y <= "0100"; when "1101" => y <= "0010"; when "1110" => y <= "0001"; when others => null; end case; (on for 3 clock cycle) for yL in 1 to 3 loop yellowL : delay port map (d, clk, q); yL <= yL + 1; end loop; (after 3 clock cycle the yellow light will be off) case r is when "0111" => y <= "0000"; when others => null; end case; (this part will on 3 red traffic light and off one red traffic light) case r is when "0111" => r <= "1011"; when "1011" => r <= "1101"; when "1101" => r <= "1110"; when "1110" => r <= "0111"; when others => null; end case; end if; end process; end behav;  :D ..hmm..thats it..my traffic light that i think it should work as i think..:o

[Altera_Forum]

Hello, 

 I saw now, that you defined gL as a bit array, apparently to act as a shift register. In this case, a delay line construct could be like this:  for I in 1 to 15 loop gL(I+1) <= gL(I); end loop;  As a shorter equivalent, you could also write gL(16 downto 2) <= gL(15 downo 1);  gL(1) has to be loaded somewhere in code (it's uninitialized now) and gL(16) is the delayed signal. The delay line construct must not necessary be executed conditionally in the case structure. But that's up to you, depending on the intended overall function. If you are intending a simple on-delay rather than a delay line, this could be achieved more simple by a delay counter.  Regards, Frank

[Altera_Forum]

thanks for the reply Frank.. 

 for the loop statement, is that it will loop for 15 clock cycle without interfering other signal?  i don't care the result from the loop as long as the signals (whatever signal) before the loop statement is remain at it state for 15 clock cycle..

[Altera_Forum]

No, a loop statement in VHDL is only a method to create parallel structures. All iterations are effectively executed simultanously at every clock cycle. For this reason the single line, multiple bit assignment is equivalent to the loop construct. If you want to delay an action in a state machine, create a delay counter, that is running down in a delay state, advance state machine afterwards.

[Altera_Forum]

i see that frank..thanks..then, i should create another vhdl file act as delay counter and make it as a component in the main code..and~ we'll see the result..

[Altera_Forum]

its not work..same error appear same as usual..here is the lines.. 

 gDelay: counterDelay port map (d, clk, q); yDelay: counterDelay port map (d, clk, q);  and..the error are.. Error (10500): VHDL syntax error at allT.vhd(54) near text "port"; expecting "(", or "'", or "." Error (10500): VHDL syntax error at allT.vhd(54) near text ";"; expecting ":=", or "<=" Error (10500): VHDL syntax error at allT.vhd(80) near text "port"; expecting "(", or "'", or "." Error (10500): VHDL syntax error at allT.vhd(80) near text ";"; expecting ":=", or "<="  this is the declaration..   architec... signal d, q : std_logic_vector(3 downto 0); component counterDelay port(D : in std_logic_vector(3 downto 0); clk : in std_logic; Q : out std_logic_vector(3 downto 0)); end component; begin  and here is the component code.. library ieee; use ieee.std_logic_1164.all; entity counterDelay is port(D : in std_logic_vector(3 downto 0); clk : in std_logic; Q : out std_logic_vector(3 downto 0)); end counterDelay; architecture dbehav of counterDelay is begin process(D, clk) begin if (clk'event AND clk = '1') then if D = 15 then for i in 1 to 15 loop Q <= D; end loop; elsif D = 3 then for i in 1 to 3 loop Q <= D; end loop; end if; end if; end process; end dbehav;  :confused:

[Altera_Forum]

Hello, 

 basically you have to stop your sequence state machine for a while  case r is when "0111" => r <= "1011"; when "1011" => r <= "1101"; when "1101" => r <= "1110"; when "1110" => r <= "0111"; when others => null; end case;  I would embed the delay counter directly to the state maschine, but that's a matter of taste.   CASE state IS WHEN S1 => timer <= conv_unsigned(10,4); WHEN S_WAIT => IF timer = 0 THEN state <= S_UP; ELSE timer <= timer - 1; END IF; WHEN S_UP =>  Basically I would use named states rather than defining state variable coding myself. Did you notice, that Quartus has a template function in HDL editor context menu? It also includes FSM examples with usual VHDL syntax.  Regards, Frank

[Altera_Forum]

thanks again frank.. 

 in your code.. CASE state IS WHEN S1 => timer <= conv_unsigned(10,4); WHEN S_WAIT => IF timer = 0 THEN state <= S_UP; ELSE timer <= timer - 1; END IF; WHEN S_UP =>  what kind of signal is for 'timer'?

[Altera_Forum]

Hello, 

 timer is unsigned(3 downto 0) here, for this reason conv_unsigned is used to assign an integer value. There are other options, too. Obviously, the size has to be adjusted according to your requirements.  Regards, Frank

[Altera_Forum]

frank..finally i've manage to finish designing my traffic light..thanks for ur advice..but the code is really mess..:p 

 i'll take my time to clear it..:D   library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity allTnew is port (clk : in std_logic; input : buffer std_logic_vector(1 to 4); g, y, r : out std_logic_vector(1 to 4); reset : in std_logic); end entity; architecture behavT of allTnew is signal timer : std_logic_vector(3 downto 0); type state_type is (s1, s2, s4, s5, s7, s8); signal state : state_type; begin process (clk, reset, input) begin if reset = '1' then state <= s1; input <= "0111"; elsif (clk'event AND clk = '1') then timer <= (others => '0'); case state is when s1 => if input = "0111" then g <= "1000"; y <= "0000"; r <= input; state <= s2; elsif input = "1011" then g <= "0100"; state <= s2; elsif input = "1101" then g <= "0010"; state <= s2; elsif input = "1110" then g <= "0001"; state <= s2; end if; when s2 => if timer = "0100" then state <= s4; g <= "0000"; else timer <= timer + 1; end if; when s4 => if input = "0111" then y <= "1000"; state <= s5; elsif input = "1011" then y <= "0100"; state <= s5; elsif input = "1101" then y <= "0010"; state <= s5; elsif input = "1110" then y <= "0001"; state <= s5; end if; when s5 => if timer = "0010" then state <= s7; y <= "0000"; else timer <= timer + 1; end if; when s7 => if input = "0111" then r <= "1011"; state <= s8; elsif input = "1011" then r <= "1101"; state <= s8; elsif input = "1101" then r <= "1110"; state <= s8; elsif input = "1110" then r <= "0111"; state <= s8; end if; when s8 => if input = "0111" then input <= "1011"; state <= s1; elsif input = "1011" then input <= "1101"; state <= s1; elsif input = "1101" then input <= "1110"; state <= s1; elsif input = "1110" then input <= "0111"; state <= s1; end if; end case; end if; end process; end behavT;  now its time to make the report for my assigment..:D

[Altera_Forum]

Hi.. i'm wondering if you can explain some of your codes to me.. especially this part..: 

 when s1 =>  if input = "0111" then  g <= "1000";  y <= "0000";  r <= input;  state <= s2;  elsif input = "1011" then  g <= "0100";  state <= s2;  elsif input = "1101" then  g <= "0010";  state <= s2;  elsif input = "1110" then  g <= "0001";  state <= s2;  end if;    when s2 =>  if timer = "0100" then  state <= s4;  g <= "0000";  else  timer <= timer + 1;  end if;     when s4 =>  if input = "0111" then  y <= "1000";  state <= s5;   elsif input = "1011" then  y <= "0100";  state <= s5;   elsif input = "1101" then  y <= "0010";  state <= s5;   elsif input = "1110" then  y <= "0001";  state <= s5;   end if;    when s5 =>  if timer = "0010" then  state <= s7;  y <= "0000";  else  timer <= timer + 1;  end if;     when s7 =>  if input = "0111" then  r <= "1011";   state <= s8;   elsif input = "1011" then  r <= "1101";  state <= s8;   elsif input = "1101" then  r <= "1110";   state <= s8;   elsif input = "1110" then  r <= "0111";   state <= s8;   end if;     when s8 =>  if input = "0111" then  input <= "1011";   state <= s1;   elsif input = "1011" then  input <= "1101";   state <= s1;   elsif input = "1101" then  input <= "1110";   state <= s1;   elsif input = "1110" then  input <= "0111";  state <= s1;   end if;    end case;

[Altera_Forum]

What is it that you don't understand in this code? 

Take a good VHDL book and look for the case and if statements.