Stratix III: Problem with Row I/O CLK2p ... output

[Altera_Forum]

Dear all 

 I'm trying to output a clock on the combined "Row I/O, CLK2p, DIFFIO_RX_L15p, DIFFOUT_L29p" pad "U28" on my Stratix III EP3SL70 device.    Although Quartus notes no problem, the pad never drives the output. The fitter reporting shows a direct output path, so this should be fine. Is there any additional assignment I have to set or are there limitations in the use of such combined pins? Or is it a problem putting an "internal" clock to a combined output pad with (in this application unused) clock input functionality? Putting the signal on a different pin works fine, however, this doesn't help in my application...   Anyone had similar issues? Any hint is very welcome!   Regards, Peter

[Altera_Forum]

The standard pin function is (single ended) IO, so it's supposed to work. I see two possible explanations: 

- The pin isn't connected in your hardware - A pin specific Quartus bug First the pin connection should be checked, e.g. by using the pin as input.

[Altera_Forum]

Already tried this, and I was not able to read the input (and the signal was reportedly there on the net...). Actually, the behaviour is the same on several boards, and a test with external pull-up / pull-down resistors showed different behaviour with the pin used as FPGA input and output, so I don't expect any soldering or conectivity problems on my boards...

[Altera_Forum]

Problem solved! 

 I found out that the signed-off documents (schematic/layout) do not match with what the board suppliert delivered (by measuring on an unassembled board i got recently). The pin in question was simply not connected.   Thanks anyway for the help trials... ;-)