How to reference hierarchy nodes in QII using Verilog

[Altera_Forum]

I'm trying to keep redudant logic. Obviously, simply setting "remove redudant logic" off doesn't work. So instead, I want to try to access the outputs from multiple instances of the redudant logic, and just make a dummy output purely to keep the optimization out of the way. Here is what I did: 

 parameter NUM_OF_DANGLING_LOADS=5; dff1 dummy_reg[NUM_OF_DANGLING_LOADS-1:0](.d(reg1out), .q(dummy_out), .clk(clock), .reset(dummy_reset));  initial begin for (i=0; i<NUM_OF_DANGLING_LOADS; i=i+1)  and and2(dummy_out, dummy_reg[i].q, dummy_out); end  QII compiler Error (10207): Verilog HDL error: can't resolve reference to object "q"  However, in QII help, it states that it supports hierarchical names: "Hierarchical Names  Supported. No references to objects outside the current module or to objects in a generate-for hierarchy."  It's not the for loop that caused the error. I tried this and it didn't work either:  dff reg1(.d(datain), .q(reg1out), .clk(clock)); assign dummy_out = reg1.q;  Same error. Anyone knows how to reference hierarchy nodes in QII using Verilog?

[Altera_Forum]

Also turn off remove duplicate registers. If that doesn't do it, it's probably due to something else. And if you have the same logic written twice, why do you want it kept? (They're can be fanout-distance issues, but that's for closing timing, which adding logic structures too isn't going to help.) 

 You don't reference the .q, you use the signal already hooked up to it, dummy_out[i].

[Altera_Forum]

I need to keep some dummy logic there just for some testing purpose.  

 Thanks for the tip. Now I wonder why I wanted to reference .q in the first place.

[Altera_Forum]

Is it dummy logic(that doesn't feed anything and therefore gets removed), or is it redundant logic? Turning off remove redundant logic will not do anything for logic that gets trimmed because it's not being used. 

There are assignments to keep logic from getting trimmed(I think it's a keep attribute). Another "trick" is to put the logic into a design partition. Part of the rules of a partition is that all IO have to be kept. For example, if you have an output of your partition that is not being used, it still has to be there because maybe on your next compile it does get used, and since that partition could be post-synthesis or post-fit(i.e. not resynthesized), we have to keep all inputs and outputs available for future use. So if you put your logic in a hierarchy and put it into a partition, that should keep it. (Note that within that partition, all nets you want kept must feed an IO of the partition. If they don't feed anything connecting to the IO of the partition, they can be removed since there is nothing that can be done outside of the partition that would cause them to be hooked up.)

[Altera_Forum]

Thanks for your suggestion, Rysc. Ideally I want some dummy logic (no output). But QII removes them even if I use the keep attribute. Now my target is to have a minimal output (just one) and keep all the dummy logic. Maybe WYSIWYG can help if I explicitly use LCELL or FF low level logic.

[Altera_Forum]

I've never used it, but a while back the "Preserve Fan-out Free Register Node" assignment was added to the Assignment Editor. It is for preserving a register that doesn't drive anything for purposes like simulation. 

  The on-line help for the assignment:    --- Quote Start ---  Preserve Fan-out Free Register Node logic option   -------------------------------------------------------------------------------- This option can be set in the Assignment Editor.    A logic option that specifies that the register should be preserved in the design even when it becomes fan-out free.  This option is available for supported device (Arria GX, Cyclone II, Cyclone III, HardCopy II, MAX II, Stratix II, and Stratix III) families.      Scripting Information   Keyword: preserve_fanout_free_node  Settings: on | off  --- Quote End ---  

[Altera_Forum]

Thanks Brad. Using preserve_fanout_free_node works!

[Altera_Forum]

Hi. How can I set that property in the Assignment Editor? 

 Thanks.