VHDL SPI Interface

Altera_Forum · ‎02-07-2011

Hello,

I made my own PCB with a Cyclone III, a simple DAC controlled with a SPI bus and I use Quartus II 10.1 with VHDL.

The board is working but now i'm trying to connect to the DAC with a SPI bus. I would like to use the FPGA as master.

Could someone please help me connecting to the DAC with SPI?

Frans.

Altera_Forum · ‎02-08-2011

Are you using a CPU such as Nios, or just HDL?

There is a SPI master available in SOPC builder, but if you are making your own HDL, it may be easier to do your own SPI master. The SPI bus is one of the simplest serial buses that exist... you just have a clock, a select signal that must be valid during the transfer and a shift register that holds the data.

Altera_Forum · ‎02-09-2011

Thank you for your reply,

I will try to make my own VHDL program for a SPI bus. When I managed to do so, I will post it here so other people might find it usesful.

Frans.

Altera_Forum · ‎02-09-2011

Dear Daixiwen,

I'm a hardware engineer having some difficulties programming my DAC with a shift register. Could you please help me find my way a little bit?

I just need to transfer 16 bits serial. For example, how can I just put 1111 1111 1111 1111 on an output serially on a clock.

Altera_Forum · ‎02-10-2011

You can find many examples of HDL SPI master / slave code with explanations just searching it on google.

Altera_Forum · ‎02-10-2011

Something like below. For slower speed, the clock pin would be set in the code as well.

signal sr : std_logic_vector (15 downto 0);
//...
if rising_edge(clk) then
  if load = '1' then
    sr <= data;
  else
    sr <= sr(14 downto 0) & '0';
  end if;
end if;
out_pin <= sr(15);

Altera_Forum · ‎02-10-2011

Thanks,

I managed to get the DAC working but what is the meaning of:

else

sr <= sr(14 downto 0) & '0';

Altera_Forum · ‎02-11-2011

it is a left bit shifting. You are replacing the 15 most significant bits from sr by its 15 least significant bits, and pad with an extra '0'.