How to implement 5 SPI-4.2 inteface in Stratix-4

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

How to implement 5 SPI-4.2 inteface in Stratix-4

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I need to implement my design in S-4 or S-3 which contains 5 SPI-4.2 interface. From the handbook, I noticed that only 4 SPI-4.2 interfaces are supported.

I am wondering what the limitation is. Is this limited by the number of DPA blocks or High Speed LVDS IO?

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