Re: Cyclone III Fails configuration on some of my boards!?!

Altera_Forum · ‎04-10-2009

I searched for a similar thread, but didn't find quite this same problem, so I registered and thought I'd ask the community for some help.

I've been developing a Cyclone III system for a few months now, and we have our own boards back. In the test harness, they work nicely. I can JTAG them, and flash the EPCS16 AS configuration. (The device is an EP3C16M164I7... the itty bitty MBGA.) However, our board isn't really meant to be JTAG'd in the end application, so when we remove our board from its test harness that gives us JTAG and just put a copy of the EPCS16 onto it, it fails configuration. i.e. we get a fresh board that's never been JTAG'd and put a copy of the good EPCS16 on it, and when that new board boots, it fails.

On the O-scope, I see about 36.16 uSec of data coming across the AS SPI configuration bus, and then it stops. It's only about 100KB of data by my back of the envelope math. That's FAR FAR less than what I see when I put the scope on the EPCS16 of the board that's in the test harness.

Something is obviously halting the configuration. We've cloned the "good" EPCS16, and we've even desoldered and swapped the EPCS16s, yet the behavior stays with the board, and not the device.

We were brainstorming, wondering if the bitfile is somehow linked to the Device ID through some setting I haven't found. (I was using compressed bitstream.)

It could also be a bad board, but I'm hoping that's not the case. I'd like to exhaust all other options before I conclude that.

The system involves a NiosII as well. It boots out of the EPCS16 after the Cyclone III configs itself. (Probably old hat to all of you guys.) That all works correctly on the first board.

Also, I've watched the FPGA CONF_DONE pin come high on both boards. (10k pullup to P3V3.) Just on one board the whole configuration transaction is WAY too short.

Does anyone know the intricacies of Cyclone III configuration and have any input? Thanks a lot.

p.s. <-----Hey look at me over there... the newest member. My name up in lights. LOL.

Altera_Forum · ‎04-10-2009

Generally. I would rather try to verify the EPCS image through JTAG on the failing board than desoldering the device. As an advantage, you can test also the EPCS to FPGA interface. I don't know, how easily you can attach a JTAG interface at the board for test. As you see, it's meaningful to have the option with any production board.

If the image (and the interface as well) verify correctly, there are still many possible reasons for configuration failure. You'll find some hints in the device manual, e.g. non-monotonic rise of configuration related supply voltages. I presume, that the configuration interface is designed according to the Altera suggestions and doesn't involve extra circuitry.

If there are no device or assembly defects causing configuration failure, it must be expected, that the connected test adapter is necessary for configuration, e.g. by it's capacitive load to the AS interface. If so, the effect should be reproducable and can be traced stepwise.

Altera_Forum · ‎04-10-2009

Thanks for the reply. We're a security company and the devices we build end up getting security bits burned, and JTAG interfaces aren't available after it's all assembled. (In this case, it's pinned out to pogo pads, which are potted over and made unavailable.) The "debug" board was all splayed out, and when we put one together as it really would be used, the config issues started up. :(

The assembly process for the final device would be to program the EPCS on an external programmer... solder it down, and pot the whole board with an epoxy for physical security. It makes it kind of hard to debug at that point, and that's what I'm dealing with today. I'm leaning toward thinking it's an assembly issue or board yield issue. But I don't want to rule anything out and waste boards.

Thanks again for the reply and help.

Altera_Forum · ‎04-10-2009

O.K., it's a bit more complicated this way. To my opinion, CIII to EPCS interface is very reliable, I never faced any problems either in development or production. Issues have been reported for cases, where the Altera circuit suggestions have been ignored or couldn't been kept for particular reasons.

Altera_Forum · ‎03-09-2010

Hey i am new to this site. I am designing a 32*32 TCAM in verilog. can any on send me a behavioral code in verilog for the same as i am facing some problem in it.

Altera_Forum · ‎04-08-2011

Not that this helps fix the issue (sorry), but I see the same problem with an EP3C16 booting from an EPCS4.

AS configuration via the dedicated header is OK, as is JTAG .jic file up load and extraction.

I'm thinking clock issue, where the .jic system runs ok at 10Mhz, but AS configuration fails to complete at 30Mhz, however I don't have a fast enough scope to see any issue with the clock.

NN