Timing fails with two TSE MACs

Altera_Forum · ‎02-24-2010

Hi everyone,

I'm working on a DBC3C40 board and I'm building a system based on the TripleSpeedEthernet sample.

I need to use both Ethernet PHYs available on the board, so I added a second TSE MAC in SOPC with all the other required interfaces.

The problem is that I obtain a timing critical warning:

"Timing requirements for slow timing analysis were not met"

In the detailed report I see the problem is due to clock hold for pll1:

slack=-2.345ns, required time=50MHz(20ns)

I tried to route the clock nets in a different way, for example:

- driving the second MAC clock with another pll output

- using another clock pin and pll for driving the second MAC, or even both

In any case the clock hold delay slightly changes but I always have a timing failure.

The final result is that the Nios software doesn't work: usually it recognizes the Ethernet link but then everything gets stuck just when I start sending data over the Ethernet port; sometimes neither the Ethernet link can be established.

Thank you for any help

Regards

Altera_Forum · ‎02-24-2010

Sorry, but I posted some wrong information

Actually the timing issue is present with the single TSE MAC, too, but in this case all works fine.

Is this normal? or should I work to avoid the timing warning?

Second point: why the first MAC stops working and the whole system gets stuck whenever I add the second MAC?

Maybe an error in the connection to the Nios, base addresses or interrupts?

Note that so far I'm not really using the second MAC, neither I initialize it; the Nios app is exactly the same. I simply added it in SOPC builder, generated and recompiled the fpga core and rebuilt syslib and application.

I think I made some silly mistake but I'm a very beginner and I can't find out it.

Regards

Altera_Forum · ‎04-22-2010

Hi SEILASER,

have you solved the two MAC problem? I encounter the similar issue now.

I work on the Stratix III dev-board. With single mac under MII the sss example works fine. After I a second mac for a quadphy hsmc card added, the first mac no longer works, but the second works.

Even when I physically isolate the second mac from the outside world (no pin assignment for the second mac), the first mac still does'nt work. that's weird...

I've got the same timing issue before and after adding the second mac.

Regards.

Altera_Forum · ‎04-22-2010

Yes, I solved the problem and now I have my board fully operating with the two MACs.

Actually the timing warning was not an issue.

The problem was with the software driver.

I found that I had to manually add the two tse devices in my application; while it seems that when there is a single one it is added automatically.

I'm using Nichestack and MicriumOS, so I don't know if this always applies for tse driver or is OS specific.

This is what I added in the very beginning of my main() function.


   alt_tse_system_mac          sys_mac =    {TSE_SYSTEM_MAC(TSE1_MAC)};
    alt_tse_system_sgdma        sys_sgdma =  {TSE_SYSTEM_SGDMA(SGDMA_TX, SGDMA_RX)};
    alt_tse_system_desc_mem     sys_mem =    {TSE_SYSTEM_DESC_MEM(DESCRIPTOR_MEMORY)};
    alt_tse_system_shared_fifo  sys_sfifo =  {TSE_SYSTEM_NO_SHARED_FIFO()}; 
    alt_tse_system_phy          sys_phy =    {TSE_SYSTEM_PHY(1, NULL)};
    alt_tse_system_mac          sys_mac2 =   {TSE_SYSTEM_MAC(TSE2_MAC)};
    alt_tse_system_sgdma        sys_sgdma2 = {TSE_SYSTEM_SGDMA(SGDMA2_TX, SGDMA2_RX)};
    alt_tse_system_desc_mem     sys_mem2 =   {TSE_SYSTEM_DESC_MEM(DESCRIPTOR_MEMORY2)};
    
  alt_tse_system_add_sys(&sys_mac,  &sys_sgdma,  &sys_mem,  &sys_sfifo, &sys_phy );
  alt_tse_system_add_sys(&sys_mac2, &sys_sgdma2, &sys_mem2, &sys_sfifo, &sys_phy );

Regards

Cris

Altera_Forum · ‎04-22-2010

Thank you for your quick reply.

although it seems that we have different problem here.

I've solved the missing device issue. I simply modified the drivers\src\altera_avalon_tse_system_info.c. The driver offers MACRO for add ing new devices.

Regards.