VHDL Code

[Altera_Forum]

Hello Guys 

I write this code with the max plus II. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;  entity axelaration_div is port (  in_divider : in integer range 0 to 2097151;  clk : in std_logic;  start : in std_logic;  out_divider : out integer range 0 to 2097151 ); end;  architecture arc_axelaration_div of axelaration_div is   signal div_num : integer range 0 to 65535 ;  signal cntr_01s : integer range 0 to 2400000;  signal cntr_ax : integer range 0 to 63;  signal flag_reset_div_num : std_logic;  signal flag_cntr_01s : std_logic;  begin  process (start)   begin  if rising_edge(start) then  if flag_reset_div_num ='1' then  div_num <= 5000;  end if;  end if;  end process;   process (clk)  begin  if rising_edge(clk) then  cntr_01s <= cntr_01s + 1;  end if;  end process;   process (clk)  begin  if falling_edge(clk) then  if flag_cntr_01s = '1' then  if cntr_01s = 2399999 then  cntr_01s <= 0;  cntr_ax <= cntr_ax + 1;  end if;  if cntr_ax = 3 then  cntr_ax <= 0;  div_num <= div_num - 1000;  end if;  if div_num = 2000 then  div_num <= in_divider;  end if;  end if;  --else   --out_divider <= div_num;  end if;  end process; out_divider <= div_num; end arc_axelaration_div;  I got an error message error: line 19: file c:\documents: unsupported feature error: unresolved signal is multiply driven What is this mean and how i can fix this Error? Thanks  Amirster

[Altera_Forum]

You are driving the integer type signals "cntr_01s" and "div_num" from more than one process. The compiler can't determine which one of them that should set the signal value. 

 Integer is not a "resolved" type and cannot be driven by more than one driver. Solve the problem by doing all assignments inside the same process.  Some signal types such as "std_logic" are resolved types. They will be evaluated if there are more than one driver process. Example driving an 'Z' and a '1' will resolve a '1' , driving a '1' and a '0' will resolve in an 'X'. This kind of usage is mostly used for test benches and simulation.  Different synthesizers and FPGA architecture handles resolved types differently too. Xilinx for example have FPGAs with tri-state buses internally, Altera doesn't.   /BitBuster

[Altera_Forum]

There are still many errors. Input ports can't be used to drive signals(the 9th clause from the last, "div_num <= in_divider;" will be a VHDL syntax error). 

 I feel this code is very confused. I don't know what time sequece or logic are you want to realize. I think this is your homework, and you are a student.  You can send me an E-mail. I'd like to study it.