Pin assignment conflict with Stratix II GX

[Altera_Forum]

I've been working on a design project in Quartus (which I'm not extraordinarily familiar with) and am having some difficulties with assigning pinouts for a Stratix II GX on a transceiver development board. When I finished my top block design, I received a clean compile. I looked up the pinouts for the board I'm working with and tried assigning the transmit and receive differential inputs, but then when I compiled again I received the following errors: 

 Error: Cannot place GXB Central Control Unit "alt2gxb0:inst|alt2gxb:alt2gxb_component|channel_quad[0].cent_unit" in target device because of its constraints  Error: Cannot place I/O "RX_2" in location Pin_Y1 because the location assignment requires GXB Central Control Unit "alt2gxb0:inst|alt2gxb:alt2gxb_component|channel_quad[0].cent_unit" to be placed in location GXBCMU_X89_Y43_N0, but GXB Central Control Unit "alt2gxb0:inst|alt2gxb:alt2gxb_component|channel_quad[0].cent_unit" has a conflict location assignment GXBCMU_X89_Y26_N0  I took a look at the pinout report generated by the fitter, and when I don't specify any pins to the RX or TX nodes, they are automatically assigned to pins that have X and Y locations corresponding to those given in the error message. So what it looks like to me is that Quartus is automatically assigning those nodes to certain pins, and when I try to assign them to pins located on a different bank it gets angry for having them defined in two places at once. This is problematic as I need to have those pins assigned to those specific locations. Any ideas as to why Quartus is automatically assigning those pinouts?  Oh, and I already went through as many of the basic debug steps as I could. The device is properly assigned (EP2SGX90EF1152C3), the pins are defined for the correct I/O standard (1.5-V PCML), and all outputs/inputs other than the RX/TX lines have been properly assigned.  Also, I apologize if this is posted in the wrong section, but I wasn't entirely sure if this was an issue with Quartus or with the Stratix II GX FPGA I'm using.

[Altera_Forum]

You may have locked the internal placement of entities in addition to the i/o pins. Open the assignment editor (CNTL-SHIFT-A) then use the "Category" pulldown to set the category to "All - Locations". Scroll through the spreadsheet of assignments; you should see pin assignments (net name then "PIN_") but no internal assignments. If there are internal assignments then delete them. Close the assignment editor (say "Yes" to saving changes when prompted) and recompile. This should resolve the conflicting assignment which attempted to lock a gigabit transceiver (GXB) to a set internal location that was contradictory to the assigned pin locations.

[Altera_Forum]

--- Quote Start ---  If there are internal assignments then delete them.  --- Quote End ---    If you're not sure you want to delete an assignment permanently, just disable it. With the Assignment Editor open, use "View --> Customize Columns" and display the "Enabled" column.

[Altera_Forum]

Unfortunately, there appear to be no internal assignments. The only assigned pin locations I can see are those that I have assigned myself.

[Altera_Forum]

I ever used the same FPGA and I remenber I set outputs of cdr(for example:rx_dataout) as virtual pins(because you only have a top design, and it is a black box), otherwise Quartus would report errors, which I didn't understand. You can try it.

[Altera_Forum]

J just run into the same problem as JWillsUT. 

Does anybody has/found/know a solution?  Thanks for your help!  damc