Problem with SDRAM and block schematic

[Altera_Forum]

I have a system with SDRAM controller core to connect to SDRAM chip on DE2 board. I know I will need to connect a PLL to the SDRAM clock signal, however I cannot figure out how to do this from my block schematic file. If I create a PLL from megafunction, how can I integrate it with my system? 

 I have attached the top level block schematic diagram. If any other files are needed I will be happy to provide  Chase

[Altera_Forum]

--- Quote Start ---  I have a system with SDRAM controller core to connect to SDRAM chip on DE2 board. I know I will need to connect a PLL to the SDRAM clock signal, however I cannot figure out how to do this from my block schematic file. If I create a PLL from megafunction, how can I integrate it with my system?  I have attached the top level block schematic diagram. If any other files are needed I will be happy to provide  Chase  --- Quote End ---    Hi,  when generating a PLL with the megawizard a symbol for the PLL is also generated. You only have to double-click into your schematic and in the opening window you should find your symbol under the "project" directory.   Kind regards  GPK

[Altera_Forum]

Yes I have the symbol. But at the top level of my design where I insert the symbol I have no means of connecting the output to the DRAM_CLK signal which is internal to the SOPC system. How can I access this signal from outside the system?

[Altera_Forum]

any of you guys know how to this (implementing the SDRAM memory) using DSP builder??? Please I nedd some help here!!!

[Altera_Forum]

--- Quote Start ---  Yes I have the symbol. But at the top level of my design where I insert the symbol I have no means of connecting the output to the DRAM_CLK signal which is internal to the SOPC system. How can I access this signal from outside the system?  --- Quote End ---    Hi,  I'm not an expert for the SOPC builder, but I think it should be possible to insert the PLL inside the SOPC builder.  Kind regards  GPK

[Altera_Forum]

True there is a PLL SOPC component. I have heard it has problems from other forum posts. It is worth a shot though so that is what I will try next

[Altera_Forum]

Hi there, if you are using the SDRAM Controller Core, then I think you are missing a pin. I have made you a little sketch, how I would suggest to wire the design. See the attachment.  

 I would use the PLL external and use the locked output to reset the core, so you can be sure a valid clk-signal is present. I would then use the "regular" clk to drive the cpu and your controller. The "phase shifted" clock goes directly to the SDRAM. So you will have to find the pin of the FPGA which is connected to the clock pin of the sdram on the de2 and output the shifted clk by this to the sdram.   This is just an example for the normal controller, if you are using the DDR controller I think it is different. Then I would suggest to look into the installationpath under ../altera/ip/../nios2eds/examples/vhdl/.. to find an example for a system with ram.  Good luck.

[Altera_Forum]

Ok i set up my system just like you have shown. A picture is attached. I searched the SDRAM datasheet and Quartus compilation report for pertinent time values and performed the phase shift calculation as it is demonstrated in the ALTPLL Megafunction guide. I used the value I calculated as the phase shift for the SDRAM clock and still I am getting the following error when I try to run program code . 

 Verifying 00800000 ( 0%) Verify failed between address 0x800000 and 0x80D62F Leaving target processor paused  Also I still get the following warnings...  Warning: Tri-state node(s) do not directly drive top-level pin(s) Warning: Converted the fan-out from the tri-state buffer "first_nios2_system:inst|sdram:the_sdram|zs_dq[15]" to the node "first_nios2_system:inst|sdram:the_sdram|za_da ta[15]" into an OR gate (Continues with an entry for each data and address pin for SDRAM  Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "SDRAM_cke" is stuck at VCC  Fast Input Register sdram za_data[0] ON Compiler or HDL Assignment  There is an entry for each data bit on the sdram. When I check the ignored timing assignments I see this entry...  Cut Timing Path On * data_in_d1 first_nios2_system_reset_clk_0_domain_synch_module No timing path applicable to specified source and destination  I have tried everything to get some type of offchip memory to work on my DE2 board and have yet to succeed. Help Please :/

[Altera_Forum]

Here is the picture of my system 

 -Chase

[Altera_Forum]

That is how I would have wired it. As the PLL I would suggest 50Mhz and -3ns Phase shift. You can easily find many threads for the DE2 here in the forum suggesting this values. Perhaps post a picture of your sopc sytem and describe your SDRAM settings. Have you got the chipselect and banks right? 

 !!!I forgot to mention one thing, your dq pin must be bidirectional. You can read dq to and from the ... so your pin allows only to give data to the sdram, but not getting something, change that accordingly. It's the green connection at the cpu!!!  Yours, Peter.

[Altera_Forum]

Great! The bidirectional output fixed my problem. Thank you I was beginning to wonder if I would ever get it working. 

 Chase